公开(公告)号：US07307471B2

公开(公告)日：2007-12-11

申请号：US11213477

申请日：2005-08-26

申请人： Gordon Gammie ,  Alice Wang ,  Uming U. Ko ,  David B. Scott

发明人： Gordon Gammie ,  Alice Wang ,  Uming U. Ko ,  David B. Scott

IPC分类号： G05F1/565

CPC分类号： H03K19/0008 ,  H03K19/00384

摘要： A device for adaptively controlling a voltage supplied to circuitry in close proximity to the device, comprising a processing module and a first tracking element coupled to the processing module. The first tracking element produces a first value indicative of a first estimated speed associated with the circuitry. The device also comprises a second tracking element coupled to the processing module. The second tracking element produces a second value indicative of a second estimated speed associated with the circuitry. The processing module compares each of the first and second values to respective target values and causes a voltage output to be adjusted based on the comparisons. The first and second tracking elements comprise a plurality of transistors, at least some of the transistors selectively provided with a transistor bias voltage to adjust transistor speed.

摘要翻译： 一种用于自适应地控制提供给设备附近的电路的电压的装置，包括耦合到处理模块的处理模块和第一跟踪元件。 第一跟踪元件产生指示与电路相关联的第一估计速度的第一值。 该装置还包括耦合到处理模块的第二跟踪元件。 第二跟踪元件产生指示与电路相关联的第二估计速度的第二值。 处理模块将第一和第二值中的每一个与各自的目标值进行比较，并且基于比较使得电压输出被调整。 第一和第二跟踪元件包括多个晶体管，至少一些晶体管选择性地提供晶体管偏置电压以调整晶体管速度。

公开(公告)号：US20100103760A1

公开(公告)日：2010-04-29

申请号：US12258747

申请日：2008-10-27

申请人： Hugh T. Mair ,  Robert L. Pitts ,  Alice Wang ,  Sumanth K. Gururjarao ,  Ramaprasath Vilangudipitchai ,  Gordon Gammie ,  Uming Ko

发明人： Hugh T. Mair ,  Robert L. Pitts ,  Alice Wang ,  Sumanth K. Gururjarao ,  Ramaprasath Vilangudipitchai ,  Gordon Gammie ,  Uming Ko

IPC分类号： G11C5/14 ,  G11C8/00

CPC分类号： G11C5/147

摘要： Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.

摘要翻译： 提供了内存电源管理系统和方法。 本发明的一个实施例包括存储器电源管理系统。 该系统包括第一低压差（LDO）调节器，其提供从第一电源电压导出的有源工作电压，以在激活模式期间为存储器阵列供电。 该系统还包括第二LDO调节器，其提供从第二电源电压导出的最低存储器保持电压，以在待机模式下为存储器阵列供电，其中第二电源电压还为至少一个外围电路供电以从其读取和/ 或写入存储器阵列。

公开(公告)号：US20050194592A1

公开(公告)日：2005-09-08

申请号：US11045222

申请日：2005-01-28

申请人： Hugh Mair ,  Gordon Gammie ,  Alice Wang

发明人： Hugh Mair ,  Gordon Gammie ,  Alice Wang

IPC分类号： H01L29/04

CPC分类号： G11C5/147

摘要： A device for adaptively controlling a voltage supplied to circuitry in substantially close proximity to the device, comprising a processing module, a first tracking element coupled to the processing module and producing a first value indicative of a first estimated speed associated with the circuitry, and a second tracking element coupled to the processing module and producing a second value indicative of a second estimated speed associated with the circuitry. The processing module compares each of the first and second values to a target value and causes a voltage output to be adjusted based on said comparison.

摘要翻译： 一种用于自适应地控制提供给基本上靠近设备的电路的电压的装置，包括处理模块，耦合到处理模块的第一跟踪元件，并产生指示与电路相关联的第一估计速度的第一值，以及 第二跟踪元件耦合到所述处理模块并产生指示与所述电路相关联的第二估计速度的第二值。 处理模块将第一和第二值中的每一个与目标值进行比较，并且基于所述比较使电压输出被调整。

公开(公告)号：US08302047B2

公开(公告)日：2012-10-30

申请号：US12766643

申请日：2010-04-23

申请人： Dennis Darcy Buss ,  Alice Wang ,  Gordon Gammie ,  Jle Gu ,  Rahul Jagdish Rithe ,  Satyendra R. P. Raju Datla ,  Sharon Hsiao-Wei Chou

发明人： Dennis Darcy Buss ,  Alice Wang ,  Gordon Gammie ,  Jle Gu ,  Rahul Jagdish Rithe ,  Satyendra R. P. Raju Datla ,  Sharon Hsiao-Wei Chou

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： H03G9/025 ,  G10L19/00 ,  H03G7/007 ,  H03G9/00 ,  H03G9/005

摘要： A method is described for simulating the f-sigma timing path delay of an integrated circuit design when local transistor variations determine the stochastic delay. This is achieved by determining an estimated delay time for a first timing path using non-linear operating point analysis of local variations (NLOPALV). An operating point is calculated for each cell that is included in a timing path in the integrated circuit design. The f-sigma operating point of a cell-arc is a point on the cell-arc delay function (CADF). An f-sigma delay value is determined for each cell using the selected operating point on the CADF of the cell. The determined delay values of the plurality of cells in the timing path may then be combined to predict the estimated delay for the entire timing path. The method may be extended to deal with slew rate, predict hold time statistics, prune paths, and deal with convergent paths.

摘要翻译： 描述了当本地晶体管变化确定随机延迟时模拟集成电路设计的f-sigma定时路径延迟的方法。 这通过使用局部变化（NLOPALV）的非线性工作点分析来确定第一定时路径的估计延迟时间来实现。 为集成电路设计中的定时路径中包含的每个单元计算工作点。 电池弧的f-σ工作点是电池电弧延迟功能（CADF）上的一个点。 使用小区的CADF上的所选择的操作点为每个小区确定f-sigma延迟值。 然后可以将定时路径中的多个小区的确定的延迟值组合以预测整个定时路径的估计延迟。 该方法可以扩展以处理压摆率，预测保持时间统计，修剪路径和处理收敛路径。

公开(公告)号：US20110216619A1

公开(公告)日：2011-09-08

申请号：US13106612

申请日：2011-05-12

申请人： Hugh T. Mair ,  Robert L. Pitts ,  Alice Wang ,  Sumanth K. Gururjarao ,  Ramaprasath Vilangudipitchai ,  Gordon Gammie ,  Uming Ko

发明人： Hugh T. Mair ,  Robert L. Pitts ,  Alice Wang ,  Sumanth K. Gururjarao ,  Ramaprasath Vilangudipitchai ,  Gordon Gammie ,  Uming Ko

IPC分类号： G11C5/14

CPC分类号： G11C5/147

摘要： Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.

摘要翻译： 提供了内存电源管理系统和方法。 本发明的一个实施例包括存储器电源管理系统。 该系统包括第一低压差（LDO）调节器，其提供从第一电源电压导出的有源工作电压，以在激活模式期间为存储器阵列供电。 该系统还包括第二LDO调节器，其提供从第二电源电压导出的最低存储器保持电压，以在待机模式下为存储器阵列供电，其中第二电源电压还为至少一个外围电路供电以从其读取和/ 或写入存储器阵列。

公开(公告)号：US07793119B2

公开(公告)日：2010-09-07

申请号：US11643194

申请日：2006-12-21

申请人： Gordon Gammie ,  Alice Wang ,  Hugh Thomas Mair

发明人： Gordon Gammie ,  Alice Wang ,  Hugh Thomas Mair

IPC分类号： G06F1/00 ,  G06F1/32 ,  G06F17/50

CPC分类号： G06F1/26

摘要： One embodiment of the present invention includes an adaptive voltage scaling system associated with an integrated circuit (IC). The system comprises at least one target performance circuit comprising a first semiconductor material and being configured to determine at least one voltage potential in response to achieving a target performance based on an applied voltage. The system also comprises a controller configured to set an output of a variable power supply to the determined at least one voltage potential, and an aging controller configured to control the at least one target performance circuit to age the first semiconductor material at a rate that is at least substantially commensurate with a rate at which other circuitry in the IC ages.

摘要翻译： 本发明的一个实施例包括与集成电路（IC）相关联的自适应电压缩放系统。 该系统包括至少一个目标性能电路，其包括第一半导体材料并被配置为响应于基于所施加的电压实现目标性能来确定至少一个电压电位。 该系统还包括控制器，该控制器被配置为将可变电源的输出设置为所确定的至少一个电压电位;以及老化控制器，其被配置为控制所述至少一个目标性能电路以使所述第一半导体材料以 至少基本上与IC中的其它电路的寿命相当。

公开(公告)号：US20090039952A1

公开(公告)日：2009-02-12

申请号：US11947012

申请日：2007-11-29

申请人： Alice Wang ,  Hugh T. Mair ,  Gordon Gammie ,  Uming Ko

发明人： Alice Wang ,  Hugh T. Mair ,  Gordon Gammie ,  Uming Ko

IPC分类号： G05F1/10 ,  G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/78

摘要： A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.

摘要翻译： 一种方法包括解析集成电路的设计以定义自动功率选通电源域中的单元，从集成电路的解析设计中自动创建自动电源门控功率域网表，以及将自动电源门控功率域网表放置和布线 生成集成电路的布局。 解析将集成电路的高级电源域分成一个或多个自动电源门控电源域。 自动功率门控功率域具有基本上零周期的上电时间，从而实现透明操作。 此外，自动电源门控功率域可以自动插入到集成电路的设计中，从而减轻集成电路设计人员插入电源域和相关硬件和软件的任务。

公开(公告)号：US07920020B2

公开(公告)日：2011-04-05

申请号：US12814195

申请日：2010-06-11

申请人： Alice Wang ,  Hugh T. Mair ,  Gordon Gammie ,  Uming Ko

发明人： Alice Wang ,  Hugh T. Mair ,  Gordon Gammie ,  Uming Ko

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： G06F17/5045 ,  G06F2217/78

摘要： A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.

摘要翻译： 一种方法包括解析集成电路的设计以在自动功率选通电源域中定义单元，从集成电路的解析设计中自动创建自动电源门控功率域网表，以及将自动电源门控功率域网表放置和布线 生成集成电路的布局。 解析将集成电路的高级电源域分成一个或多个自动电源门控电源域。 自动功率门控功率域具有基本上零周期的上电时间，从而实现透明操作。 此外，自动电源门控功率域可以自动插入到集成电路的设计中，从而减轻集成电路设计人员插入电源域和相关硬件和软件的任务。

公开(公告)号：US20100287517A1

公开(公告)日：2010-11-11

申请号：US12766643

申请日：2010-04-23

申请人： Dennis Darcy Buss ,  Alice Wang ,  Gordon Gammie ,  Jie Gu ,  Rahul Jagdish Rithe ,  Satyendra R.P. Raju Datla ,  Sharon Hsiao-Wei Chou

发明人： Dennis Darcy Buss ,  Alice Wang ,  Gordon Gammie ,  Jie Gu ,  Rahul Jagdish Rithe ,  Satyendra R.P. Raju Datla ,  Sharon Hsiao-Wei Chou

IPC分类号： G06F17/50

CPC分类号： H03G9/025 ,  G10L19/00 ,  H03G7/007 ,  H03G9/00 ,  H03G9/005

摘要： A method is described for simulating the f-sigma timing path delay of an integrated circuit design when local transistor variations determine the stochastic delay. This is achieved by determining an estimated delay time for a first timing path using non-linear operating point analysis of local variations (NLOPALV). An operating point is calculated for each cell that is included in a timing path in the integrated circuit design. The f-sigma operating point of a cell-arc is a point on the cell-arc delay function (CADF). An f-sigma delay value is determined for each cell using the selected operating point on the CADF of the cell. The determined delay values of the plurality of cells in the timing path may then be combined to predict the estimated delay for the entire timing path. The method may be extended to deal with slew rate, predict hold time statistics, prune paths, and deal with convergent paths.

摘要翻译： 描述了当本地晶体管变化确定随机延迟时模拟集成电路设计的f-sigma定时路径延迟的方法。 这通过使用局部变化（NLOPALV）的非线性工作点分析来确定第一定时路径的估计延迟时间来实现。 为集成电路设计中的定时路径中包含的每个单元计算工作点。 电池弧的f-σ工作点是电池电弧延迟功能（CADF）上的一个点。 使用小区的CADF上的所选择的操作点为每个小区确定f-sigma延迟值。 然后可以将定时路径中的多个小区的确定的延迟值组合以预测整个定时路径的估计延迟。 该方法可以扩展以处理压摆率，预测保持时间统计，修剪路径和处理收敛路径。

公开(公告)号：US07760011B2

公开(公告)日：2010-07-20

申请号：US11947012

申请日：2007-11-29

申请人： Alice Wang ,  Hugh T. Mair ,  Gordon Gammie ,  Uming Ko

发明人： Alice Wang ,  Hugh T. Mair ,  Gordon Gammie ,  Uming Ko

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： G06F17/5045 ,  G06F2217/78

摘要： A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software.

摘要翻译： 一种方法包括解析集成电路的设计以在自动功率选通电源域中定义单元，从集成电路的解析设计中自动创建自动电源门控功率域网表，以及将自动电源门控功率域网表放置和布线 生成集成电路的布局。 解析将集成电路的高级电源域分成一个或多个自动电源门控电源域。 自动功率门控功率域具有基本上零周期的上电时间，从而实现透明操作。 此外，自动电源门控功率域可以自动插入到集成电路的设计中，从而减轻集成电路设计人员插入电源域和相关硬件和软件的任务。