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13 条记录 (耗时 0.019 秒)

    Method of operating a crossbar switch
    1.
    发明授权
    Method of operating a crossbar switch 有权
    操纵交叉开关的方法

    公开(公告)号：US07089346B2

    公开(公告)日：2006-08-08

    申请号：US10378365

    申请日：2003-03-03

    申请人： Markus Cebulla ,  Gottfried Andreas Goldrian ,  Bernd Leppla ,  Norbert Schumacher

    发明人： Markus Cebulla ,  Gottfried Andreas Goldrian ,  Bernd Leppla ,  Norbert Schumacher

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4022

    摘要： The present invention relates to a method of operating a crossbar switch (1) having a control logic (2) and n input ports (i—0, . . . , i_n-1) and m output ports (o—0, . . . , o_m-1), wherein information packets of p different priority levels are routed from said n input ports (i—0, . . . , i_n-1) to said m output ports (o—0, . . . , o_m-1). Within said control logic (2), a pool (CRA) of buffers (CRA—0, CRA—1, . . . ) is provided for each crosspoint (4) for temporarily storing address information related to said information packets.

    摘要翻译： 本发明涉及一种操作具有控制逻辑（2）和n个输入端口（i-1，...，i_n-1）的交叉开关（1）的方法和m个输出端口 （0≤0.0，...，o_m-1），其中p个不同优先级的信息分组从所述n个输入端口（i 0 - ...，i_n-1）到所述m个输出端口（0〜... 0，...，o_m-1）。 在所述控制逻辑（2）内，为每个交叉点（4）提供缓冲器（CRA < - > 0，CRA - - 1等）的池（CRA） 用于临时存储与所述信息分组相关的地址信息。

    Chip circuit for combined and data compressed FIFO arbitration for a non-blocking switch
    5.
    发明授权
    Chip circuit for combined and data compressed FIFO arbitration for a non-blocking switch 失效
    用于非阻塞开关的组合和数据压缩FIFO仲裁的片状电路

    公开(公告)号：US07675930B2

    公开(公告)日：2010-03-09

    申请号：US12033867

    申请日：2008-02-19

    申请人： Francois Abel ,  Gottfried Andreas Goldrian ,  Ingemar Holm ,  Helmut Kohler ,  Norbert Schumacher

    发明人： Francois Abel ,  Gottfried Andreas Goldrian ,  Ingemar Holm ,  Helmut Kohler ,  Norbert Schumacher

    IPC分类号： H04L12/54

    CPC分类号： H04L49/90 ,  H04L2012/5679

    摘要： A system for switching data packets through a multiple (m) input, multiple (n) output switching device providing switching having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped.

    摘要翻译： 一种用于通过多输入（n）输出切换装置切换数据分组的系统，其提供具有快速单周期吞吐量的切换。 相应的交换设备的行为类似于从多个输入端口（IP）读取输入输入控制信息的一组分布式输出队列的输出排队交换机，并以允许与相应输出端口（...）容易关联的形式来压缩信息 OP），单个输入端口临时映射到该端口。

    Combined and data compressed FIFO based arbitration for a non-blocking switch
    6.
    发明授权
    Combined and data compressed FIFO based arbitration for a non-blocking switch 失效
    用于非阻塞开关的组合和数据压缩基于FIFO的仲裁

    公开(公告)号：US07379470B2

    公开(公告)日：2008-05-27

    申请号：US10425133

    申请日：2003-04-28

    申请人： Francois Abel ,  Gottfried Andreas Goldrian ,  Ingemar Holm ,  Helmut Kohler ,  Norbert Schumacher

    发明人： Francois Abel ,  Gottfried Andreas Goldrian ,  Ingemar Holm ,  Helmut Kohler ,  Norbert Schumacher

    IPC分类号： H04L12/54

    CPC分类号： H04L49/90 ,  H04L2012/5679

    摘要： A method and system for switching data packets through a multiple (m) input, multiple (n) output switching device providing a switching method having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped.

    摘要翻译： 一种用于通过多输入（n）输出切换装置切换数据分组的方法和系统，其提供具有快速一周期吞吐量的切换方法。 相应的交换设备的行为类似于从多个输入端口（IP）读取输入输入控制信息的一组分布式输出队列的输出排队交换机，并以允许与相应输出端口（...）容易关联的形式来压缩信息 OP），单个输入端口临时映射到该端口。

    Method of switching between a first and second clock signal by establishing a trigger time in which both signals are considered to be substantially in-phase
    7.
    发明授权
    Method of switching between a first and second clock signal by establishing a trigger time in which both signals are considered to be substantially in-phase 失效
    通过建立两个信号被认为是基本上同相的触发时间来在第一和第二时钟信号之间切换的方法

    公开(公告)号：US06633991B1

    公开(公告)日：2003-10-14

    申请号：US09572170

    申请日：2000-05-17

    申请人： Gottfried Andreas Goldrian

    发明人： Gottfried Andreas Goldrian

    IPC分类号： G06F112

    CPC分类号： G06F1/08 ,  H03K5/26 ,  H03L7/00

    摘要： A system and method for observing the two clocking phase signals, finding a point in time when said signals have a phase coincidence which is good enough for fulfilling a phase difference requirement (e.g. 20 ps), and switching from one clock source to the other. The essential idea is not to compare the phases directly but to generate an auxiliary signal out of the two clock signals which is easier to handle in order to find that desired point in time and which reflects all desired properties of the time dependent phase shift between said clock signals. At a predetermined location in the cycle of both clock signals (e.g. its positive transition) a pulse is generated out of each of the clock signals with matched identical delay elements located very close to each other on the same chip for both signals. As they match they produce exactly the same pulse widths. The absolute length of the pulse width is of minor relevance as long as the length of the pulses is the same within close limits. Both signals are ANDed. Thus, in the resulting signal a pulse emerge at every positive transition of the oscillator clocks when the phase alignment of the clock signals is closer than the width of the transition pulse. When the alignment is bad—no signal will be produced.

    摘要翻译： 一种用于观察两个时钟相位信号的系统和方法，找到所述信号具有相当于足以实现相位差要求（例如20ps）以及从一个时钟源切换到另一个的时间点的时间点。 基本思想不是直接比较相位，而是在两个时钟信号之间产生辅助信号，这两个时钟信号更容易处理，以便找到期望的时间点，并且反映所述时间相关相移之间的所有期望的性质 时钟信号。 在两个时钟信号（例如其正转换）的周期中的预定位置处，每个时钟信号产生一个脉冲，其中匹配的相同的延迟元件在两个信号的同一芯片上彼此非常接近。 当它们匹配时，它们产生完全相同的脉冲宽度。 只要脉冲的长度在接近的范围内是相同的，脉冲宽度的绝对长度才具有很小的相关性。 两个信号均为AND。 因此，在产生的信号中，当时钟信号的相位对准比转换脉冲的宽度更近时，脉冲在振荡器时钟的每个正转变处出现。 当对准不好时，不会产生信号。

    Digital frequency correction
    8.
    发明授权
    Digital frequency correction 失效
    数字频率校正

    公开(公告)号：US06665809B1

    公开(公告)日：2003-12-16

    申请号：US09573015

    申请日：2000-05-17

    申请人： Gottfried Andreas Goldrian ,  Thomas Anthony Gregg

    发明人： Gottfried Andreas Goldrian ,  Thomas Anthony Gregg

    IPC分类号： G06F104

    CPC分类号： G04G7/00 ,  G06F1/14 ,  H04J3/0697

    摘要： The basic idea comprised of the present invention is to decentralize the generation of time information without suffering from the cost disadvantages expectable due to use of prior art techniques necessary for synchronizing and correcting a plurality instead of only one or two of time suppliers caused by said decentralization. This is achieved by the approach not to readjust the oscillator(s), but, instead, to accept the inaccuracy of the physical device ‘oscillator’ but to measure its inaccuracy and to correct it with the aid of a continuos correction calculation which is advantageously done in a digital way under usage of ETS input information and system oscillator output information.

    摘要翻译： 由本发明构成的基本思想是分散时间信息的产生，而不会因为使用现有技术技术所需的成本缺点而不会因同步和纠正多个而不是由所述分散产生的时间供应商中的一个或两个 。 这是通过不重新调整振荡器的方法实现的，而是接受物理设备的振荡器的不准确性，而是借助于有利的连续校正计算来测量其不准确性并进行校正 在使用ETS输入信息和系统振荡器输出信息的情况下以数字方式完成。

    Mechanism for receiving messages at a coupling facility
    9.
    发明授权
    Mechanism for receiving messages at a coupling facility 失效
    在耦合设备接收信息的机制

    公开(公告)号：US5706432A

    公开(公告)日：1998-01-06

    申请号：US474574

    申请日：1995-06-07

    申请人： David Arlen Elko ,  Gottfried Andreas Goldrian ,  Steven Neil Goss ,  Thomas Anthony Gregg ,  Audrey Ann Helffrich ,  Joseph Arthur Williams

    发明人： David Arlen Elko ,  Gottfried Andreas Goldrian ,  Steven Neil Goss ,  Thomas Anthony Gregg ,  Audrey Ann Helffrich ,  Joseph Arthur Williams

    IPC分类号： G06F13/12 ,  G06F15/17 ,  G06F15/167

    CPC分类号： G06F13/126 ,  G06F15/17

    摘要： Computer system processing complexes which can operate actually or apparently synchronously and in parallel or asynchronously in a network have a coupling facility for sending and receiving commands, responses, and data. The memory for the central processing complexes (which is accessible to each of the processing elements) is provided with storage for messages and data for coupling over a communication channel interface. Each of a plurality of processing elements (CPC) has data objects used to maintain state information for shared data in the coupling facility storage. The coupling facility can receive both message commands and data, sending data and responses to messages, and sending and receiving secondary messages. The processing element accessible memory provides a state information buffer control information operation memory block for describing the hardware communication environment associated with the computer system mechanism for storage of state information pertaining to a communications buffer residing in said coupling facility storage. The communication channel has a set of address registers. The system employs four new instructions, PREPARE CHANNEL BUFFER, SIGNAL CHANNEL BUFFER, MOVE CHANNEL BUFFER DATA, and TEST CHANNEL BUFFER, to enable a coupling facility control program to directly manipulate the address registers and control the flow of data, commands and responses between the coupling-facility storage and communication channels for the central processing elements. This provides a direct interface between the coupling facility and an intersystem communication channel for the receipt of messages and data and the related receiving functions.

    摘要翻译： 可以在网络中实际或明显同步并行或异步操作的计算机系统处理复合体具有用于发送和接收命令，响应和数据的耦合设备。 用于中央处理复合体（每个处理元件可访问）的存储器提供有用于通过通信信道接口耦合的消息和数据的存储。 多个处理元件（CPC）中的每一个具有用于维持耦合设备存储器中共享数据的状态信息的数据对象。 耦合设施可以接收消息命令和数据，发送数据和对消息的响应，以及发送和接收辅助消息。 处理元件可访问存储器提供状态信息缓冲器控制信息操作存储器块，用于描述与计算机系统机构相关联的硬件通信环境，用于存储与驻留在所述耦合设备存储器中的通信缓冲器有关的状态信息。 通信通道具有一组地址寄存器。 该系统采用四个新的指令：PREPARE CHANNEL BUFFER，SIGNAL CHANNEL BUFFER，MOVE CHANNEL BUFFER DATA，以及TEST CHANNEL BUFFER，以实现一个耦合设备控制程序，直接操纵地址寄存器，并控制数据流，命令和响应 耦合设备存储和通信信道用于中央处理元件。 这提供了耦合设施和用于接收消息和数据以及相关接收功能的系统间通信信道之间的直接接口。

    System with intersystem information links for intersystem traffic having I/O traffic being transmitted to and from processor bus via processor means
    10.
    发明授权
    System with intersystem information links for intersystem traffic having I/O traffic being transmitted to and from processor bus via processor means 失效
    具有用于系统间流量的系统间信息链路的系统，其具有经由处理器装置向处理器总线发送和经由处理器总线的I / O流量

    公开(公告)号：US6002883A

    公开(公告)日：1999-12-14

    申请号：US696547

    申请日：1996-08-14

    申请人： Gottfried Andreas Goldrian

    发明人： Gottfried Andreas Goldrian

    IPC分类号： G06F13/36 ,  G06F12/08 ,  G06F13/42 ,  G06F15/167 ,  G06F13/00

    CPC分类号： G06F13/4226

    摘要： The exchange of commands and data between I/O devices, such as DASDs, and a computer system, preferrably a multiprocessor computer system, usually takes place via I/O adapters. The question arises of how to couple these I/O adapters to the computer system. In prior art solutions, the I/O adapters were either attached to the second level cache or to a memory bus. The present invention relates to a method of coupling the stream of I/O commands and I/O data to the computer system via the processor busses. Because of the high bandwidth of the processor busses, an additional transmission of I/O data does not disturb regular data traffic on the processor bus. One advantage of using the processor busses for the transmission of I/O data is that pins of the second level cache chips don't have to be used for the attachment of I/O adapters any more and thus become available for other purposes. For example, the bandwidths of processor busses or memory busses can be increased, or additional processor busses can be accomodated.

    摘要翻译： I / O设备（如DASD）和计算机系统（最好是多处理器计算机系统）之间的命令和数据交换通常通过I / O适配器进行。 出现了如何将这些I / O适配器耦合到计算机系统的问题。 在现有技术的解决方案中，I / O适配器被连接到第二级缓存或存储器总线。 本发明涉及一种通过处理器总线将I / O命令流和I / O数据流耦合到计算机系统的方法。 由于处理器总线的高带宽，I / O数据的附加传输不会干扰处理器总线上的常规数据流量。 使用处理器总线传输I / O数据的一个优点是，第二级缓存芯片的引脚不必再用于I / O适配器的连接，因此可用于其他目的。 例如，可以增加处理器总线或存储器总线的带宽，或者可以容纳附加的处理器总线。