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公开(公告)号：US07089346B2
公开(公告)日：2006-08-08
申请号：US10378365
申请日：2003-03-03
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： The present invention relates to a method of operating a crossbar switch (1) having a control logic (2) and n input ports (i—0, . . . , i_n-1) and m output ports (o—0, . . . , o_m-1), wherein information packets of p different priority levels are routed from said n input ports (i—0, . . . , i_n-1) to said m output ports (o—0, . . . , o_m-1). Within said control logic (2), a pool (CRA) of buffers (CRA—0, CRA—1, . . . ) is provided for each crosspoint (4) for temporarily storing address information related to said information packets.
摘要翻译： 本发明涉及一种操作具有控制逻辑（2）和n个输入端口（i-1，...，i_n-1）的交叉开关（1）的方法和m个输出端口 （0≤0.0，...，o_m-1），其中p个不同优先级的信息分组从所述n个输入端口（i 0 - ...，i_n-1）到所述m个输出端口（0〜... 0，...，o_m-1）。 在所述控制逻辑（2）内，为每个交叉点（4）提供缓冲器（CRA < - > 0，CRA - - 1等）的池（CRA） 用于临时存储与所述信息分组相关的地址信息。
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公开(公告)号：US07826434B2
公开(公告)日：2010-11-02
申请号：US11951102
申请日：2007-12-05
CPC分类号： H04L49/45 , H04L49/101 , H04L49/1523 , H04L49/90
摘要： The present invention relates to a buffered crossbar switch which provides a step of changing the size and/or number of queuing buffer entries to ensure optimum buffer memory usage independent of the size of data packets processed.
摘要翻译： 本发明涉及一种缓冲交叉开关，其提供改变排队缓冲器条目的大小和/或数量以确保最优缓冲存储器使用的步骤，独立于处理的数据分组的大小。
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公开(公告)号：US07349388B1
公开(公告)日：2008-03-25
申请号：US10334218
申请日：2002-12-30
CPC分类号： H04L49/45 , H04L49/101 , H04L49/1523 , H04L49/90
摘要： The present invention relates to a buffered crossbar switch and its method of operation which provides a step of changing the size and/or number of queuing buffer entries to ensure optimum buffer memory usage independent of the size of data packets processed.
摘要翻译： 本发明涉及一种缓冲交叉开关及其操作方法，其提供了改变排队缓冲器条目的大小和/或数量以确保最佳缓冲存储器使用的步骤，而与处理的数据分组的大小无关。
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公开(公告)号：US06909710B1
公开(公告)日：2005-06-21
申请号：US10331369
申请日：2002-12-30
CPC分类号： H04L49/101 , H04L49/1523 , H04L49/252 , H04L49/3009
摘要： The present invention relates to a method of operating a buffered crossbar switch. The proposed method reduces power dissipation in a buffered crossbar switch by reducing the number of crossbar buffer write processes.
摘要翻译： 本发明涉及一种操作缓冲交叉开关的方法。 所提出的方法通过减少交叉开关缓冲器写入过程的数量来减少缓冲交叉开关中的功耗。
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5.发明授权Chip circuit for combined and data compressed FIFO arbitration for a non-blocking switch 失效用于非阻塞开关的组合和数据压缩FIFO仲裁的片状电路公开(公告)号：US07675930B2
公开(公告)日：2010-03-09
申请号：US12033867
申请日：2008-02-19
IPC分类号： H04L12/54
CPC分类号： H04L49/90 , H04L2012/5679
摘要： A system for switching data packets through a multiple (m) input, multiple (n) output switching device providing switching having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped.
摘要翻译： 一种用于通过多输入（n）输出切换装置切换数据分组的系统，其提供具有快速单周期吞吐量的切换。 相应的交换设备的行为类似于从多个输入端口（IP）读取输入输入控制信息的一组分布式输出队列的输出排队交换机，并以允许与相应输出端口（...）容易关联的形式来压缩信息 OP），单个输入端口临时映射到该端口。
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6.发明授权Combined and data compressed FIFO based arbitration for a non-blocking switch 失效用于非阻塞开关的组合和数据压缩基于FIFO的仲裁公开(公告)号：US07379470B2
公开(公告)日：2008-05-27
申请号：US10425133
申请日：2003-04-28
IPC分类号： H04L12/54
CPC分类号： H04L49/90 , H04L2012/5679
摘要： A method and system for switching data packets through a multiple (m) input, multiple (n) output switching device providing a switching method having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped.
摘要翻译： 一种用于通过多输入（n）输出切换装置切换数据分组的方法和系统，其提供具有快速一周期吞吐量的切换方法。 相应的交换设备的行为类似于从多个输入端口（IP）读取输入输入控制信息的一组分布式输出队列的输出排队交换机，并以允许与相应输出端口（...）容易关联的形式来压缩信息 OP），单个输入端口临时映射到该端口。
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公开(公告)号：US07197540B2
公开(公告)日：2007-03-27
申请号：US10093920
申请日：2002-03-08
IPC分类号： G06F15/167
CPC分类号： G06F15/17393 , H04L49/101 , H04L49/1546 , H04L49/25 , H04L49/3018 , H04L49/3027
摘要： The present invention relates to switching technology in computer networks and in particular to a method and system for switching information packets through a m input, n output device. According to the invention it is proposed to temporarily buffer said packets according to a new, self-explanatory, preferred a linear addressing scheme in which a respective buffer location of consecutive stream packets results from a respective self-explanatory, or linear, respectively, incrementation of a buffer pointer. Preferably, a matrix of FIFO storage elements (10,11,12,13) having an input and an output crossbar can be used for implementing input/output paralleling modes (ILP,OLP) and multiple lanes and achieving address input/output scaling up to a single cycle.
摘要翻译： 本发明涉及计算机网络中的切换技术，特别涉及一种通过m输入输出设备切换信息分组的方法和系统。 根据本发明，提出根据一种新的，不言自明的优选的线性寻址方案临时缓冲所述分组，其中连续流分组的相应缓冲器位置分别由相应的不说明的或线性的递增 的缓冲区指针。 优选地，可以使用具有输入和输出交叉开关的FIFO存储元件（10,11,12,13）的矩阵来实现输入/输出并行模式（ILP，OLP）和多个通道，并且实现地址输入/输出放大 到一个周期。
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公开(公告)号：US07269158B2
公开(公告)日：2007-09-11
申请号：US10378410
申请日：2003-03-03
IPC分类号： H04L12/28
CPC分类号： H04L49/254 , H04L47/50 , H04L49/101 , H04L49/1523 , H04L49/205 , H04L49/3027
摘要： Apparatus and method of operating a crossbar switch (1) having a control logic, an output port scheduler (2), n input ports (i—0, . . . , i—31) and m output ports (o—0, . . . , o—31), wherein information packets are routed from said n input ports to said m output ports, and wherein said output port scheduler (2) controls the sequence of packets output at said output ports (o—0, . . . , o—31). To ensure fairness regarding packet transfer/routing and the packet sequence, an input port number corresponding to the input port a new information packet is arriving at is stored in round-robin mode in a port number buffer (pnb—0). For output, said input port number is retrieved from said port number buffer (pnb—0) in round robin mode, too, and with this port number, address information regarding the packet is obtained from a control logic buffer of the crossbar switch (1).
摘要翻译： 操作具有控制逻辑的交叉开关（1）的装置和方法，输出端口调度器（2），n个输入端口（i，...， SUB> 31）和m个输出端口（o < - > 0，...，o - 31），其中信息包从所述n个输入端口路由到所述m个输出端 端口，并且其中所述输出端口调度器（2）控制在所述输出端口（0〜... 0，...，o→31）处输出的分组序列。 为了确保关于分组传送/路由和分组序列的公平性，对应于新信息分组到达的输入端口的输入端口号以循环模式存储在端口号缓冲器（pnb < - SUB > 0）。 对于输出，在循环模式中从所述端口号缓冲器（pnb < - > 0）检索所述输入端口号，并且利用该端口号，从控制逻辑获得关于分组的地址信息 交叉开关（1）的缓冲器。
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公开(公告)号：US07145873B2
公开(公告)日：2006-12-05
申请号：US09965588
申请日：2001-09-27
CPC分类号： H04L47/2441 , H04L49/103 , H04L49/3018 , H04L49/3027 , H04L49/3045 , H04L49/508
摘要： The invention proposes a switching arrangement for transporting data packets which comprise a data packet destination information and a payload, to one or more output ports. The switching device is able to route the arriving data packets according to the data packet destination information, to at least one dedicated of the output ports. It comprises at each input port an input buffer with at least as many single input queues as there are output ports, and an input controller for each input port, serving for controlling the order of multiplexing the data packets from the input queues of the corresponding input buffer to the switching device. The total of input ports is divided up into several subsets of input ports. Each subset in the switching device has its separate output buffer for storing at addresses therein at least the payload of each data packet arriving at the input port. At least one set of as many output queues as the switching arrangement has output ports are arranged. In these output queues at least the address of each payload stored in the output buffer is stored, sorted according to the data packet destination information. The stored payload is then deliverable to its dedicated at least one output port under use of the stored addresses.
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公开(公告)号：US07107490B2
公开(公告)日：2006-09-12
申请号：US10313326
申请日：2002-12-06
IPC分类号： G06F11/00
CPC分类号： G06F11/261
摘要： The present invention relates to a method and system for testing error detection programs dedicated for detecting hardware failures in a computer system, in which error case patterns comprising stimuli values are generated and response patterns to the hardware are evaluated. In order to develop and debug such error detection programs already at an early phase during hardware development it is proposed to feed a simulation model (26) of said hardware with said error patterns, and after running said model, evaluating (12) the model response patterns generated by the simulation model and comparing the response patterns with those expected as a result of the error detection program.
摘要翻译： 本发明涉及用于检测专用于检测计算机系统中的硬件故障的错误检测程序的方法和系统，其中产生包括刺激值的错误情况模式并评估对硬件的响应模式。 为了在硬件开发过程中早期阶段开发和调试这种错误检测程序，建议用所述错误模式来提供所述硬件的仿真模型（26），并且在运行所述模型之后，评估（12）模型响应 仿真模型生成的模式，并将响应模式与错误检测程序的结果进行比较。
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