公开(公告)号：US20080164930A1

公开(公告)日：2008-07-10

申请号：US11649434

申请日：2007-01-04

申请人： Gregory Jason Rausch

发明人： Gregory Jason Rausch

IPC分类号： G06F1/04

CPC分类号： H03H11/20 ,  H03K5/13 ,  H03K5/15013 ,  H03K2005/00052 ,  H03K2005/00267 ,  H03L7/06 ,  H03L7/0812 ,  H03L7/0998

摘要： A phase interpolator circuit may comprise a multiplexer circuit (MUX) to receive a plurality of clock signals at MUX inputs and to output a first clock signal and a second clock signal that are out of phase with each other, a digital to analog converter circuit (DAC) to convert a digital input to first and second DAC output currents such that a sum of the first and second DAC output currents comprises a substantially constant current value, and a weighted averager circuit coupled to the MUX and the DAC. The weighted averager circuit may operate to sum weighted first and second clock signals and to output a phase interpolated clock signal. The first clock signal may be weighted according to the first DAC output current and the second clock signal may be weighted according to the second DAC output current. Other apparatus, systems, and methods are disclosed.

摘要翻译： 相位插值器电路可以包括多路复用器电路（MUX），用于在MUX输入端接收多个时钟信号，并输出彼此不同相的第一时钟信号和第二时钟信号，数模转换器电路 DAC）将数字输入转换为第一和第二DAC输出电流，使得第一和第二DAC输出电流的总和包括基本上恒定的电流值，以及耦合到MUX和DAC的加权平均器电路。 加权平均器电路可以操作以加权加权的第一和第二时钟信号并输出​​相位内插的时钟信号。 可以根据第一DAC输出电流对第一时钟信号进行加权，并且可以根据第二DAC输出电流对第二时钟信号进行加权。 公开了其他装置，系统和方法。

公开(公告)号：US07532053B2

公开(公告)日：2009-05-12

申请号：US11649434

申请日：2007-01-04

申请人： Gregory Jason Rausch

发明人： Gregory Jason Rausch

IPC分类号： H03H11/16

CPC分类号： H03H11/20 ,  H03K5/13 ,  H03K5/15013 ,  H03K2005/00052 ,  H03K2005/00267 ,  H03L7/06 ,  H03L7/0812 ,  H03L7/0998

摘要： A phase interpolator circuit may comprise a multiplexer circuit (MUX) to receive a plurality of clock signals at MUX inputs and to output a first clock signal and a second clock signal that are out of phase with each other, a digital to analog converter circuit (DAC) to convert a digital input to first and second DAC output currents such that a sum of the first and second DAC output currents comprises a substantially constant current value, and a weighted averager circuit coupled to the MUX and the DAC. The weighted averager circuit may operate to sum weighted first and second clock signals and to output a phase interpolated clock signal. The first clock signal may be weighted according to the first DAC output current and the second clock signal may be weighted according to the second DAC output current. Other apparatus, systems, and methods are disclosed.

摘要翻译： 相位插值器电路可以包括多路复用器电路（MUX），用于在MUX输入端接收多个时钟信号，并输出彼此不同相的第一时钟信号和第二时钟信号，数模转换器电路 DAC）将数字输入转换为第一和第二DAC输出电流，使得第一和第二DAC输出电流的总和包括基本上恒定的电流值，以及耦合到MUX和DAC的加权平均器电路。 加权平均器电路可以操作以加权加权的第一和第二时钟信号并输出​​相位内插的时钟信号。 可以根据第一DAC输出电流对第一时钟信号进行加权，并且可以根据第二DAC输出电流对第二时钟信号进行加权。 公开了其他装置，系统和方法。

公开(公告)号：US07443219B2

公开(公告)日：2008-10-28

申请号：US11649435

申请日：2007-01-04

申请人： Gregory Jason Rausch

发明人： Gregory Jason Rausch

IPC分类号： H03H11/16

CPC分类号： H03H11/20 ,  H03K5/13 ,  H03K5/15013 ,  H03K2005/00052 ,  H03K2005/00267 ,  H03L7/06 ,  H03L7/0812 ,  H03L7/0998

摘要： A phase interpolator circuit may comprise a multiplexer circuit (MUX) coupled to a plurality of clock signals at MUX inputs and may provide a first clock signal and a second clock signal at MUX outputs that are out of phase with each other, a digital to analog converter circuit (DAC) to convert a digital input to first and second DAC current outputs such that a sum of the first and second DAC output currents comprises a substantially constant current value, a weighted averager circuit coupled to the MUX and the DAC, and a variable capacitive load circuit coupled to the first and second DAC current outputs. The weighted averager circuit may operate to sum weighted first and second clock signals and to output a phase interpolated clock signal, wherein the first clock signal is weighted according to a first DAC output current and the second clock signal is weighted according to a second DAC output current. Other apparatus, systems, and methods are disclosed.

摘要翻译： 相位插值器电路可以包括耦合到MUX输入处的多个时钟信号的多路复用器电路（MUX），并且可以在彼此不同相的MUX输出处提供第一时钟信号和第二时钟信号，数模转换器 转换器电路（DAC），用于将数字输入转换为第一和第二DAC电流输出，使得第一和第二DAC输出电流的和包括基本上恒定的电流值，耦合到MUX和DAC的加权平均器电路，以及 可变容性负载电路耦合到第一和第二DAC电流输出。 加权平均器电路可以操作以加权加权的第一和第二时钟信号并输出​​相位内插时钟信号，其中根据第一DAC输出电流对第一时钟信号进行加权，并且根据第二DAC输出对第二时钟信号进行加权 当前。 公开了其他装置，系统和方法。

公开(公告)号：US20080164928A1

公开(公告)日：2008-07-10

申请号：US11649435

申请日：2007-01-04

申请人： Gregory Jason Rausch

发明人： Gregory Jason Rausch

IPC分类号： H03H11/16 ,  H03K5/15

CPC分类号： H03H11/20 ,  H03K5/13 ,  H03K5/15013 ,  H03K2005/00052 ,  H03K2005/00267 ,  H03L7/06 ,  H03L7/0812 ,  H03L7/0998

摘要： A phase interpolator circuit may comprise a multiplexer circuit (MUX) coupled to a plurality of clock signals at MUX inputs and may provide a first clock signal and a second clock signal at MUX outputs that are out of phase with each other, a digital to analog converter circuit (DAC) to convert a digital input to first and second DAC current outputs such that a sum of the first and second DAC output currents comprises a substantially constant current value, a weighted averager circuit coupled to the MUX and the DAC, and a variable capacitive load circuit coupled to the first and second DAC current outputs. The weighted averager circuit may operate to sum weighted first and second clock signals and to output a phase interpolated clock signal, wherein the first clock signal is weighted according to a first DAC output current and the second clock signal is weighted according to a second DAC output current. Other apparatus, systems, and methods are disclosed.