Data transfer using frequency notching of radio-frequency signals
    1.
    发明授权
    Data transfer using frequency notching of radio-frequency signals 有权
    使用射频信号频率切换进行数据传输

    公开(公告)号:US07656963B2

    公开(公告)日:2010-02-02

    申请号:US11669027

    申请日:2007-01-30

    IPC分类号: H04L27/00

    摘要: A method for data transmission includes forming a notched radio-frequency (RF) burst according to one or more data values, where a bandwidth of the notched RF burst is at least two percent of the center frequency of the notched RF burst. Forming a notched RF pulse includes altering, according to the data, at least one of the amplitude and phase of one or more selected components, where each of the selected components has a bandwidth within the bandwidth of the notched RF burst.

    摘要翻译: 一种用于数据传输的方法包括:根据一个或多个数据值形成带隙的射频(RF)突发,其中,所述缺口的RF突发的带宽为所述有缺口的RF突发的中心频率的至少2%。 形成缺口RF脉冲包括根据数据改变一个或多个所选择的组件的幅度和相位中的至少一个,其中每个所选择的组件具有在缺口RF突发的带宽内的带宽。

    Phase interpolation apparatus, systems, and methods
    2.
    发明申请
    Phase interpolation apparatus, systems, and methods 有权
    相位插值设备,系统和方法

    公开(公告)号:US20080164930A1

    公开(公告)日:2008-07-10

    申请号:US11649434

    申请日:2007-01-04

    IPC分类号: G06F1/04

    摘要: A phase interpolator circuit may comprise a multiplexer circuit (MUX) to receive a plurality of clock signals at MUX inputs and to output a first clock signal and a second clock signal that are out of phase with each other, a digital to analog converter circuit (DAC) to convert a digital input to first and second DAC output currents such that a sum of the first and second DAC output currents comprises a substantially constant current value, and a weighted averager circuit coupled to the MUX and the DAC. The weighted averager circuit may operate to sum weighted first and second clock signals and to output a phase interpolated clock signal. The first clock signal may be weighted according to the first DAC output current and the second clock signal may be weighted according to the second DAC output current. Other apparatus, systems, and methods are disclosed.

    摘要翻译: 相位插值器电路可以包括多路复用器电路(MUX),用于在MUX输入端接收多个时钟信号,并输出彼此不同相的第一时钟信号和第二时钟信号,数模转换器电路 DAC)将数字输入转换为第一和第二DAC输出电流,使得第一和第二DAC输出电流的总和包括基本上恒定的电流值,以及耦合到MUX和DAC的加权平均器电路。 加权平均器电路可以操作以加权加权的第一和第二时钟信号并输出​​相位内插的时钟信号。 可以根据第一DAC输出电流对第一时钟信号进行加权,并且可以根据第二DAC输出电流对第二时钟信号进行加权。 公开了其他装置,系统和方法。

    Method and apparatus for adapting multi-band ultra-wideband signaling to interference sources
    6.
    发明申请
    Method and apparatus for adapting multi-band ultra-wideband signaling to interference sources 有权
    用于将多频带超宽带信令适应于干扰源的方法和装置

    公开(公告)号:US20040048574A1

    公开(公告)日:2004-03-11

    申请号:US10371064

    申请日:2003-02-20

    申请人: General Atomics

    IPC分类号: H04B015/00

    摘要: A method and apparatus for operation in a multi-frequency band system in the presence of an interference, the method comprising the steps of: receiving signaling in a plurality of wideband frequency sub-bands, each wideband frequency sub-band having a different center frequency, wherein a bandwidth of each wideband frequency sub-band is at least 2 percent of a center frequency of the wideband frequency sub-band; detecting an interfering signal having signal energy in a portion of a respective sub-band of the wideband frequency sub-bands; deciding to discontinue use of the respective sub-band; and instructing a transmitting device transmitting the signaling to transmit subsequent signaling in any except the respective sub-band of the plurality of wideband frequency sub-bands.

    摘要翻译: 一种用于在存在干扰的情况下在多频带系统中操作的方法和装置,所述方法包括以下步骤:在多个宽带频率子带中接收信令,每个宽带频率子带具有不同的中心频率 其中每个宽带频率子带的带宽是所述宽带频率子带的中心频率的至少2%; 检测在宽带频率子带的相应子带的一部分中具有信号能量的干扰信号; 决定停止使用相应的子带; 以及指示发送所述信令的发送设备,以发送除了所述多个宽带频带子带中的相应子带之外的任何信号。

    METHOD FOR SYNCHRONISING DATA CONVERTERS BY MEANS OF A SIGNAL TRANSMITTED FROM ONE TO THE NEXT

    公开(公告)号:US20180323794A1

    公开(公告)日:2018-11-08

    申请号:US15774455

    申请日:2016-11-04

    IPC分类号: H03M1/06

    摘要: In an architecture for processing data comprising a control unit and converters CNj to be synchronized to an active front of a common reference clock CLK, the synchronizing method makes provision for the converters to be arranged in at least one series chain, and for a procedure for synchronizing the converters by propagating a synchronizing signal SYNC-m emitted by the control unit, said signal being retransmitted as output OUT by each converter, after resynchronization to a clock active front, to a synchronization input IN of a following converter in the chain. Each converter comprises a synchronization configuration register REG containing at least one polarity parameter Sel-edgej that sets the polarity of the reference-clock front for reliable detection of a synchronizing signal received via the input of the converter. A phase parameter Sel-shiftj furthermore allows the phase of the sampling clocks of n converting cores of the converters, working at a sampling frequency obtained by dividing by n the CLK reference-clock frequency, to be synchronized.