公开(公告)号：US08026166B2

公开(公告)日：2011-09-27

申请号：US12190131

申请日：2008-08-12

申请人： Griselda Bonilla ,  Tien Cheng ,  Lawrence A. Clevenger ,  Stephan Grunow ,  Chao-Kun Hu ,  Roger A. Quon ,  Zhiguo Sun ,  Wei-tsui Tseng ,  Yiheng Xu ,  Yun Wang ,  Hyeok-sang Oh

发明人： Griselda Bonilla ,  Tien Cheng ,  Lawrence A. Clevenger ,  Stephan Grunow ,  Chao-Kun Hu ,  Roger A. Quon ,  Zhiguo Sun ,  Wei-tsui Tseng ,  Yiheng Xu ,  Yun Wang ,  Hyeok-sang Oh

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties and methods of making the same are provided. In one embodiment, the integrated circuit structure comprises: an interlevel dielectric layer disposed above a semiconductor substrate; a conductive interconnect embedded in the interlevel dielectric layer; a first capping layer comprising SiwCxNyHz disposed upon the conductive interconnect; a second capping layer comprising SiaCbNcHd (has less N) having a dielectric constant less than about 4 disposed upon the first capping layer; and a third capping layer comprising SiwCxNyHz disposed upon the second capping layer, wherein a+b+c+d=1.0 and a, b, c, and d are each greater than 0 and less than 1, and wherein w+x+y+z=1.0 and w, x, y, and z are each greater than 0 and less than 1.

摘要翻译： 提供包括具有低介电常数和良好氧阻隔性能的封盖层的互连结构及其制备方法。 在一个实施例中，集成电路结构包括：设置在半导体衬底之上的层间电介质层; 嵌入在所述层间电介质层中的导电互连; 包括设置在所述导电互连上的SiwCxNyHz的第一覆盖层; 包含设置在第一覆盖层上的介电常数小于约4的SiaCbNcHd（具有较小的N）的第二覆盖层; 以及第三覆盖层，其包括设置在所述第二覆盖层上的SiwCxNyHz，其中a + b + c + d = 1.0和a，b，c和d各自大于0且小于1，并且其中w + x + y + z = 1.0，w，x，y和z分别大于0且小于1。

公开(公告)号：US20100038793A1

公开(公告)日：2010-02-18

申请号：US12190131

申请日：2008-08-12

申请人： Griselda Bonilla ,  Tien Cheng ,  Lawrence A. Clevenger ,  Stephan Grunow ,  Chao-Kun Hu ,  Roger A. Quon ,  Zhiguo Sun ,  Wei-tsui Tseng ,  Yiheng Xu ,  Yun Wang ,  Hyeok-Sang Oh

发明人： Griselda Bonilla ,  Tien Cheng ,  Lawrence A. Clevenger ,  Stephan Grunow ,  Chao-Kun Hu ,  Roger A. Quon ,  Zhiguo Sun ,  Wei-tsui Tseng ,  Yiheng Xu ,  Yun Wang ,  Hyeok-Sang Oh

IPC分类号： H01L23/48

CPC分类号： H01L21/76834 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties and methods of making the same are provided. In one embodiment, the integrated circuit structure comprises: an interlevel dielectric layer disposed above a semiconductor substrate; a conductive interconnect embedded in the interlevel dielectric layer; a first capping layer comprising SiwCxNyHz disposed upon the conductive interconnect; a second capping layer comprising SiaCbNcHd (has less N) having a dielectric constant less than about 4 disposed upon the first capping layer; and a third capping layer comprising SiwCxNyHz disposed upon the second capping layer, wherein a+b+c+d=1.0 and a, b, c, and d are each greater than 0 and less than 1, and wherein w+x+y+z=1.0 and w, x, y, and z are each greater than 0 and less than 1.

摘要翻译： 提供包括具有低介电常数和良好氧阻隔性能的封盖层的互连结构及其制备方法。 在一个实施例中，集成电路结构包括：设置在半导体衬底之上的层间电介质层; 嵌入在所述层间电介质层中的导电互连; 包括设置在所述导电互连上的SiwCxNyHz的第一覆盖层; 包含设置在第一覆盖层上的介电常数小于约4的SiaCbNcHd（具有较小N）的第二覆盖层; 以及第三覆盖层，其包括设置在所述第二覆盖层上的SiwCxNyHz，其中a + b + c + d = 1.0和a，b，c和d各自大于0且小于1，并且其中w + x + y + z = 1.0，w，x，y和z分别大于0且小于1。