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    Compiler retargeting based on instruction semantic models
    1.
    发明授权
    Compiler retargeting based on instruction semantic models 有权
    基于指令语义模型的编译器重定向

    公开(公告)号：US09280326B1

    公开(公告)日：2016-03-08

    申请号：US11140353

    申请日：2005-05-26

    申请人： Gunnar Braun ,  Andreas Hoffmann ,  Volker Greive ,  Rainer Leupers ,  Jianjiang Ceng

    发明人： Gunnar Braun ,  Andreas Hoffmann ,  Volker Greive ,  Rainer Leupers ,  Jianjiang Ceng

    IPC分类号： G06F9/45 ,  G06F9/44

    CPC分类号： G06F8/37

    摘要： Generating a description of compiler code selector rules from an architecture description. A method comprises accessing a target architecture model written in an architecture description language (ADL) and extracting semantic information therefrom to generate a plurality of semantic statements. Rules that map from source code operations to semantic patterns are accessed. The semantic statements are searched for matches for the semantic patterns to generate mappings that serve as a description of compiler code selector rules.

    摘要翻译： 从架构描述生成编译器代码选择器规则的描述。 一种方法包括访问以架构描述语言（ADL）编写的目标体系结构模型，并从中提取语义信息以生成多个语义语句。 访问从源代码操作映射到语义模式的规则。 搜索语义语句用于语义模式的匹配，以生成用作编译器代码选择器规则的描述的映射。

    Generation of compiler description from architecture description
    2.
    发明授权
    Generation of compiler description from architecture description 有权
    从架构描述生成编译器描述

    公开(公告)号：US08677312B1

    公开(公告)日：2014-03-18

    申请号：US10815228

    申请日：2004-03-30

    申请人： Gunnar Braun ,  Andreas Hoffmann ,  Volker Greive

    发明人： Gunnar Braun ,  Andreas Hoffmann ,  Volker Greive

    IPC分类号： G06F9/44

    CPC分类号： G06F8/37

    摘要： A computer implemented method of generating a compiler description from an architecture description. Information is automatically extracted from an architecture description that is usable in a description of an architecture described by the architecture description. The extracted information is imported into a program comprising a graphical user interface that accepts user provided additional information that is usable in the compiler description. User provided additional information is accessed that is usable in the compiler description. A compiler description is automatically generated for the architecture described by the architecture description, based on the automatically extracted information and the accessed user provided additional information.

    摘要翻译： 一种从架构描述生成编译器描述的计算机实现的方法。 信息自动地从可用于由架构描述描述的架构的描述中使用的架构描述中提取。 所提取的信息被导入到包括图形用户界面的程序中，该图形用户界面接受用户提供的在编译器描述中可用的附加信息。 用户提供了可在编译器描述中使用的附加信息。 基于自动提取的信息和访问的用户提供的附加信息，针对由架构描述描述的架构自动生成编译器描述。

    Techniques for automatic generation of instruction-set documentation
    3.
    发明授权
    Techniques for automatic generation of instruction-set documentation 有权
    自动生成指令集文档的技术

    公开(公告)号：US08522221B1

    公开(公告)日：2013-08-27

    申请号：US13206032

    申请日：2011-08-09

    申请人： Gunnar Braun ,  Andreas Hoffmann ,  Volker Greive

    发明人： Gunnar Braun ,  Andreas Hoffmann ,  Volker Greive

    IPC分类号： G06F9/45

    CPC分类号： G06F8/73

    摘要： A method and system for the automatic generation of user guides. Specifically, the method of the present invention includes accessing an abstract processor model of a processor, wherein said abstract processor model is represented using a hierarchical architecture description language (ADL). The abstract processor model includes a plurality of instructions arranged in a hierarchical structure. An internal representation of the abstract processor model is generated by flattening the abstract processor model. The flattening process generates a plurality of rules grouped by common convergent instructions. Each rule describes an instruction path through the hierarchical structure that converges at a corresponding convergent instruction. An instruction-set documentation is automatically generated from the plurality of rules, wherein the instruction-set documentation is arranged convergent instruction by convergent instruction.

    摘要翻译： 用于自动生成用户指南的方法和系统。 具体地，本发明的方法包括访问处理器的抽象处理器模型，其中所述抽象处理器模型使用分层架构描述语言（ADL）来表示。 抽象处理器模型包括以分层结构布置的多个指令。 抽象处理器模型的内部表示是通过对抽象处理器模型进行平化来生成的。 扁平化过程产生通过公共收敛指令分组的多个规则。 每个规则描述通过分级结构的指令路径，其收敛于相应的收敛指令。 从多个规则自动生成指令集文档，其中指令集文档通过收敛指令排列收敛指令。

    Method and system for automatic generation of instruction-set documentation from an abstract processor model described using a hierarchical architectural description language
    4.
    发明授权
    Method and system for automatic generation of instruction-set documentation from an abstract processor model described using a hierarchical architectural description language 有权
    从使用层次结构描述语言描述的抽象处理器模型自动生成指令集文档的方法和系统

    公开(公告)号：US08006225B1

    公开(公告)日：2011-08-23

    申请号：US11145240

    申请日：2005-06-03

    申请人： Gunnar Braun ,  Volker Greive ,  Andreas Hoffmann

    发明人： Gunnar Braun ,  Volker Greive ,  Andreas Hoffmann

    IPC分类号： G06F9/44

    CPC分类号： G06F8/73

    摘要： A method and system for the automatic generation of instruction-set manuals. Specifically, the method of the present invention includes accessing an abstract processor model of a processor, wherein said abstract processor model is represented using a hierarchical architecture description language (ADL). The abstract processor model includes a plurality of instructions arranged in a hierarchical structure. An internal representation of the abstract processor model is generated by flattening the abstract processor model. The flattening process generates a plurality of rules grouped by common convergent instructions. Each rule describes an instruction path through the hierarchical structure that converges at a corresponding convergent instruction. An instruction-set documentation is automatically generated from the plurality of rules, wherein the instruction-set documentation is arranged convergent instruction by convergent instruction.

    摘要翻译： 一种用于自动生成指令集手册的方法和系统。 具体地，本发明的方法包括访问处理器的抽象处理器模型，其中所述抽象处理器模型使用分层架构描述语言（ADL）来表示。 抽象处理器模型包括以分层结构布置的多个指令。 抽象处理器模型的内部表示是通过对抽象处理器模型进行平化来生成的。 扁平化过程产生通过公共收敛指令分组的多个规则。 每个规则描述通过分级结构的指令路径，其收敛于相应的收敛指令。 从多个规则自动生成指令集文档，其中指令集文档通过收敛指令排列收敛指令。

    Scheduling of instructions
    6.
    发明授权
    Scheduling of instructions 有权
    调度指令

    公开(公告)号：US08689202B1

    公开(公告)日：2014-04-01

    申请号：US11096184

    申请日：2005-03-30

    申请人： Gunnar Braun ,  Andreas Hoffmann ,  Volker Grieve ,  Manuel Hohenauer ,  Rainer Leupers

    发明人： Gunnar Braun ,  Andreas Hoffmann ,  Volker Grieve ,  Manuel Hohenauer ,  Rainer Leupers

    IPC分类号： G06F9/45

    CPC分类号： G06F8/445

    摘要： A method of automatically extracting information from an architecture description. A memory resident directed acyclic graph data structure comprising nodes representing instructions and edges whose weights represent dependencies between pairs of instructions is constructed. A list of ready nodes are maintained in the directed acyclic graph. A list of nodes not scheduled is maintained. And, it is determined whether the next instruction to be scheduled is to be taken from the list of ready nodes or from the list of nodes not yet scheduled.

    摘要翻译： 一种从架构描述中自动提取信息的方法。 存储器驻留定向非循环图数据结构包括表示指令的节点和其权重表示指令对之间依赖性的边。 在有向非循环图中保留了一个可用节点列表。 维护未调度的节点列表。 并且，确定下一个要调度的指令是从准备节点的列表还是从尚未调度的节点的列表中取出。

    Method and system for instruction-set architecture simulation using just in time compilation
    7.
    发明授权
    Method and system for instruction-set architecture simulation using just in time compilation 有权
    使用即时编译的指令集架构仿真的方法和系统

    公开(公告)号：US08086438B2

    公开(公告)日：2011-12-27

    申请号：US10309554

    申请日：2002-12-03

    申请人： Achim Nohl ,  Gunnar Braun ,  Andreas Hoffmann ,  Oliver Schliebusch ,  Rainer Leupers ,  Heinrich Myer

    发明人： Achim Nohl ,  Gunnar Braun ,  Andreas Hoffmann ,  Oliver Schliebusch ,  Rainer Leupers ,  Heinrich Myer

    IPC分类号： G06F9/44 ,  G06F9/455 ,  G06F9/26 ,  G06F9/30 ,  G06F7/38 ,  G06F9/45

    CPC分类号： G06F9/45516 ,  G06F9/45504 ,  G06F17/5022

    摘要： A method of simulating a program. Compiled and interpretive techniques are combined into a just-in-time cached compiled technique. When an instruction of a program simulation is to be executed at run-time, a table of compiled instructions is accessed to determine whether compiled data for the instruction is stored in the table. If the compiled data is not therein, the instruction is compiled and stored in the table. The compiled data is returned to a simulator that is executing the program simulation. In another embodiment, before storing new information in the table, another table may be consulted to determine if the location to which the new information is to be stored is protected. If the table location is protected, the new information is not stored in the table. Rather, the new information is simply passed on to the simulator.

    摘要翻译： 一种模拟程序的方法。 编译和解释技术被组合成即时缓存编译技术。 当在运行时执行程序仿真的指令时，访问编译指令的表以确定指令的编译数据是否存储在表中。 如果编译数据不在其中，则该指令将被编译并存储在表中。 将编译的数据返回到正在执行程序仿真的模拟器。 在另一个实施例中，在将新信息存储在表中之前，可以参考另一个表来确定新信息要存储的位置是否被保护。 如果表位置受到保护，新信息不会存储在表中。 相反，新的信息只是传递给模拟器。

    Processor/memory co-exploration at multiple abstraction levels
    8.
    发明授权
    Processor/memory co-exploration at multiple abstraction levels 有权
    处理器/内存在多个抽象级别的共同探索

    公开(公告)号：US07788078B1

    公开(公告)日：2010-08-31

    申请号：US11069496

    申请日：2005-02-28

    申请人： Gunnar Braun ,  Olaf Zorres ,  Achim Nohl ,  Andreas Hoffmann

    发明人： Gunnar Braun ,  Olaf Zorres ,  Achim Nohl ,  Andreas Hoffmann

    IPC分类号： G06F17/50 ,  G01R31/28

    CPC分类号： G06F17/5022 ,  G06F2217/86

    摘要： Processor/memory co-exploration at multiple abstraction levels. An architecture description language (ADL) description of a processor/memory system is accessed. The ADL description models on one of a plurality of abstraction levels. The abstraction levels may include a functional (or bit-accurate) level and a cycle-accurate level. Further, a communication protocol for the processor/memory system is accessed. The communication protocol is formed from primitives, wherein a memory interface formed from the primitives is useable in simulation at the abstraction levels. A processor/memory simulation model is automatically generated from the description and description of the communication protocol. The processor/memory simulation model comprises a processor/memory interface comprising the primitives and based on the communication protocol. The memory interface allows simulation of the processor/memory on the appropriate abstraction level for the simulation. For example, the processor/memory interface may be a functional interface or a cycle-accurate interface.

    摘要翻译： 处理器/内存在多个抽象级别的共同探索。 访问处理器/存储器系统的架构描述语言（ADL）描述。 ADL描述模型在多个抽象级别之一上。 抽象级别可以包括功能（或比特精确）级别和循环准确级别。 此外，访问用于处理器/存储器系统的通信协议。 通信协议由原语形成，其中由原语形成的存储器接口可在抽象级别的仿真中使用。 从通信协议的描述和描述中自动生成处理器/存储器模拟模型。 处理器/存储器模拟模型包括包括原语并基于通信协议的处理器/存储器接口。 存储器接口允许在适当的抽象级别上仿真处理器/存储器进行仿真。 例如，处理器/存储器接口可以是功能接口或周期准确的接口。

    Automatic generation of structure and control path using hardware description language
    9.
    发明授权
    Automatic generation of structure and control path using hardware description language 有权
    使用硬件描述语言自动生成结构和控制路径

    公开(公告)号：US07373638B1

    公开(公告)日：2008-05-13

    申请号：US10641457

    申请日：2003-08-14

    申请人： Oliver Schliebusch ,  Andreas Hoffmann ,  Achim Nohl ,  Gunnar Braun ,  Heinrich Meyr

    发明人： Oliver Schliebusch ,  Andreas Hoffmann ,  Achim Nohl ,  Gunnar Braun ,  Heinrich Meyr

    IPC分类号： G06F9/45 ,  G06F9/44 ,  G06F17/50

    CPC分类号： G06F17/5045

    摘要： Translating to a hardware description language (HDL) from an architecture description language (ADL) is disclosed. An architecture description that is written in the ADL and has a hierarchical organization is received. Decoders are generated, described in the HDL, from the architecture description written in the ADL. Control signals are generated, described in the HDL, from the architecture description written in the ADL. The decoders are configured to output the control signals and the control signals are input to functional units in order to preserve the hierarchical organization of the architecture description written in the ADL.

    摘要翻译： 公开了从架构描述语言（ADL）翻译成硬件描述语言（HDL）。 接收到ADL中编写并具有层次结构的架构描述。 HDL中描述的解码器根据ADL中的架构描述生成。 根据ADL中写入的架构描述，在HDL中描述控制信号。 解码器被配置为输出控制信号，并且控制信号被输入到功能单元，以便保持写入ADL中的架构描述的层次结构。