公开(公告)号：US20050102483A1

公开(公告)日：2005-05-12

申请号：US11003120

申请日：2004-12-03

申请人： Ryan Kinter ,  Scott McCoy ,  Gideon Intrater

发明人： Ryan Kinter ,  Scott McCoy ,  Gideon Intrater

IPC分类号： G06F12/06 ,  G06F12/00

CPC分类号： G06F12/0684

摘要： The invention includes a method of debugging an embedded processor. Scratch pad memory of an embedded processor is accessed to form a configuration file characterizing the configuration of scratch pad regions of the scratch pad memory. The embedded processor is debugged using information from the configuration file. The invention also includes an embedded processor with a processor core and scratch pad memory connected to the processor core. The scratch pad memory includes a set of scratch pad regions. The scratch pad memory stores values characterizing base addresses and region size values of the set of scratch pad regions.

摘要翻译： 本发明包括一种调试嵌入式处理器的方法。 访问嵌入式处理器的便携式存储器以形成表征便笺式存储器的暂存区域区域的配置的配置文件。 嵌入式处理器使用配置文件中的信息进行调试。 本发明还包括具有连接到处理器核心的处理器核心和临时存储器存储器的嵌入式处理器。 便笺本式存储器包括一组暂存区域。 临时存储器存储表征该组暂存区区域的基址和区域大小值的值。

公开(公告)号：US5603017A

公开(公告)日：1997-02-11

申请号：US309546

申请日：1994-09-20

申请人： Gideon Intrater ,  Oved Oz ,  Yachin Afek

发明人： Gideon Intrater ,  Oved Oz ,  Yachin Afek

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F11/36 ,  G06F13/24 ,  G06F15/78 ,  H04L27/38 ,  G06F1/04

CPC分类号： G06F11/3648 ,  G06F11/3656 ,  G06F11/3664 ,  G06F13/24 ,  G06F15/7842 ,  G06F9/30167 ,  G06F9/32 ,  G06F9/3879 ,  H04L27/38

摘要： An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data.

摘要翻译： 集成数据处理系统包括用于传送指令和数据的共享内部总线。 共享总线接口单元连接到共享内部总线，并通过共享外部总线连接到共享外部存储器阵列，使得保存在共享外部存储器阵列中的指令和数据可经由共享总线接口单元传送到共享内部总线 。 通用（GP）中央处理单元（CPU）连接到共享内部总线，用于检索GP指令。 GP CPU包括一个执行单元，用于执行GP指令以处理由GP CPU从共享内部总线检索的数据。 连接到共享内部总线的数字信号处理器（DSP）模块，DSP模块包括用于通过执行DSP命令列表指令来处理由DSP模块接收的外部提供的数字信号的信号处理器。 DSP模块执行DSP命令列表代码指令与GP CPU执行GP指令无关，并行执行GP指令。 共享的内部存储器，其保存命令列表代码指令，并且被连接以供DSP模块访问，用于检索由DSP模块执行的命令列表代码指令，并由GP CPU访问用于存储和检索指令和数据。

公开(公告)号：US5566308A

公开(公告)日：1996-10-15

申请号：US248769

申请日：1994-05-25

申请人： Chaim Bendelac ,  Dan Biran ,  Ohad Falik ,  Gadi Erlich ,  Jonathan Levy ,  Gideon Intrater

发明人： Chaim Bendelac ,  Dan Biran ,  Ohad Falik ,  Gadi Erlich ,  Jonathan Levy ,  Gideon Intrater

IPC分类号： G06F9/32 ,  G06F9/355 ,  G06F12/00

CPC分类号： G06F9/342 ,  G06F9/32 ,  G06F9/321

摘要： A processor core for provides a linear extension of addressable memory space of a microprocessor with minimal additional hardware and software complexity. A N+x bit pointer register (e.g. program counter) holds an N+x bit instruction address. The N+x bit instruction address provides to an execution unit a pointer to an instruction in the memory to be processed by the execution unit. An encoder encodes the N+x bit address into an N bit encoding of the N+x bit address. The processor core can thereby address 2.sup.x times more memory locations than 2.sup.N. Two other registers each hold a portion of an data address (i.e. a pointer to a datum in memory to be operated on). An address former concatenates the portions of the address in the two registers to form the data address. Therefore, the address is formed from portions of the data address stored in multiple registers without performing any arithmetic on the portions.

摘要翻译： 处理器核心，用于提供微处理器的可寻址存储空间的线性扩展，同时具有最小的附加硬件和软件复杂性。 N + x位指针寄存器（例如程序计数器）保存N + x位指令地址。 N + x位指令地址向执行单元提供指向由执行单元处理的存储器中的指令的指针。 编码器将N + x位地址编码为N + x位地址的N位编码。 因此，处理器核可以处理比2N多两倍的存储单元。 另外两个寄存器分别保存数据地址的一部分（即指向要操作的存储器中的基准的指针）。 地址前缀将两个寄存器中地址的部分连接起来形成数据地址。 因此，地址由存储在多个寄存器中的数据地址的部分形成，而不对这些部分执行任何算术。

公开(公告)号：US20060036808A1

公开(公告)日：2006-02-16

申请号：US11214466

申请日：2005-08-29

申请人： Gideon Intrater ,  Anders Jagd ,  Ryan Kinter

发明人： Gideon Intrater ,  Anders Jagd ,  Ryan Kinter

IPC分类号： G06F12/00

CPC分类号： G06F9/3812 ,  G06F9/3802 ,  G06F9/3824 ,  G06F12/0848

摘要： A method and apparatus within a processing system is provided for separating access to an instruction memory and a data memory to allow concurrent access by different pipeline stages within the processing system to both the instruction memory and the data memory. An instruction memory interface is provided to access the instruction memory. A data memory interface is provided to access the data memory. Redirection logic is provided to determine whether an access by the data memory interface should be directed to the instruction memory interface utilizing either the address of the access, or the type of instruction that is executing. If the access is redirected, the access to the instruction memory is performed by the instruction memory interface, and data retrieved by the instruction memory interface is then provided to the data memory interface, and in turn to the pipeline stage within the processing system that requested the data memory interface to access the data.

公开(公告)号：US5630153A

公开(公告)日：1997-05-13

申请号：US317783

申请日：1994-10-04

申请人： Amos Intrater ,  Moshe Doron ,  Gideon Intrater ,  Lev Epstein ,  Maurice Valentaten ,  Israel Greiss

发明人： Amos Intrater ,  Moshe Doron ,  Gideon Intrater ,  Lev Epstein ,  Maurice Valentaten ,  Israel Greiss

IPC分类号： G06J3/00 ,  G06F9/38 ,  G06F15/78 ,  H04L27/00 ,  H04M11/00 ,  H04N1/40 ,  G06F9/26 ,  G06F9/40 ,  G06F9/44 ,  G06F13/36

CPC分类号： H04L27/00 ,  G06F15/7842 ,  G06F9/3885

摘要： An integrated data processing platform for processing a digital signal that includes a general purpose processor and a digital signal processor (DSP) module. The DSP module recovers digital data from a digital signal utilizing a sequence of DSP operations selected by the general purpose processor. The general purpose processor processes the digital data recovered by the DSP module, but is also available to perform general purpose tasks. A shared internal memory array selectively provides information to the DSP module and to the general purpose processor. The information stored in the internal memory array includes operands utilized in the execution of the DSP algorithm and selected instructions and data utilized by the general purpose CPU either for controlling the execution of the DSP algorithm or for executing its own general purpose tasks. While in many applications the data processing system will include an analog front end that converts a modulated input signal received on an analog transmission channel to a corresponding digital signal for processing by the data processing system, the data processing system may also receive the digital signal directly from a digital source.

摘要翻译： 一种用于处理包括通用处理器和数字信号处理器（DSP）模块的数字信号的集成数据处理平台。 DSP模块利用通用处理器选择的一系列DSP操作，从数字信号中恢复数字数据。 通用处理器处理由DSP模块恢复的数字数据，但也可用于执行通用任务。 共享内部存储器阵列选择性地向DSP模块和通用处理器提供信息。 存储在内部存储器阵列中的信息包括在DSP算法的执行中使用的操作数和通用CPU所使用的选择的指令和数据，用于控制DSP算法的执行或用于执行其自己的通用任务。 在许多应用中，数据处理系统将包括模拟前端，将模拟传输通道上接收的调制输入信号转换为相应的数字信号，以供数据处理系统处理，数据处理系统也可以直接接收数字信号 从数字来源。

公开(公告)号：US5249286A

公开(公告)日：1993-09-28

申请号：US982031

申请日：1992-11-24

申请人： Donald B. Alpert ,  Oved Oz ,  Gideon Intrater ,  Reuven Marko ,  Alon Shacham

发明人： Donald B. Alpert ,  Oved Oz ,  Gideon Intrater ,  Reuven Marko ,  Alon Shacham

IPC分类号： G06F12/12

CPC分类号： G06F12/126

摘要： A microprocessor architecture that includes capabilities for locking individual entries into its integrated instruction cache and data cache while leaving the remainder of the cache unlocked and available for use in capturing the microprocessor's dynamic locality of reference. The microprocessor also includes the capability for locking instruction cache entries without requiring that the instructions be executed during the locking process.

摘要翻译： 一种微处理器架构，其包括将单个条目锁定到其集成指令高速缓存和数据高速缓存中的能力，同时使缓存的其余部分被解锁并可用于捕获微处理器的动态参考位置。 微处理器还包括锁定指令高速缓存条目的能力，而不需要在锁定过程期间执行指令。

公开(公告)号：US6065078A

公开(公告)日：2000-05-16

申请号：US96402

申请日：1998-06-11

申请人： Ohad Falik ,  Ophir Shabtay ,  Gideon Intrater ,  Tzvia Weisman

发明人： Ohad Falik ,  Ophir Shabtay ,  Gideon Intrater ,  Tzvia Weisman

IPC分类号： G06F11/36 ,  G06F13/12 ,  G06F13/00

CPC分类号： G06F13/124

摘要： A multiprocessor system includes a plurality of processors. A debugger interface includes interface circuitry to interface the plurality of processors to a debugger. The debugger interface includes means for receiving a debugger command from the debugger. Debugger command directing means determines from the debugger command for which of at least one of the plurality of processors the debugger command is intended, directs the debugger command, via the interface circuitry to the at least one intended processor. A processor command is received from one of the plurality of processors, and processor command directing means directs the processor command, received from the one processor, via the interface circuitry to the debugger. The system is especially suited for debugging software that is executing on the plurality of processors of the multiprocessor system.

摘要翻译： 多处理器系统包括多个处理器。 调试器接口包括用于将多个处理器连接到调试器的接口电路。 调试器接口包括用于从调试器接收调试器命令的装置。 调试器命令指导装置根据调试器命令确定调试器命令的多个处理器中的至少一个处理器中的哪一个，将调试器命令经由接口电路引导到至少一个预期处理器。 从多个处理器之一接收处理器命令，并且处理器命令指示装置将从一个处理器接收的处理器命令经由接口电路引导到调试器。 该系统特别适用于在多处理器系统的多个处理器上执行的调试软件。

公开(公告)号：US5915266A

公开(公告)日：1999-06-22

申请号：US708786

申请日：1996-09-09

申请人： Ohad Falik ,  Gideon Intrater

发明人： Ohad Falik ,  Gideon Intrater

IPC分类号： G06F9/32 ,  G06F9/355 ,  G06F12/00

CPC分类号： G06F9/342 ,  G06F9/32 ,  G06F9/321

摘要： A processor core for providing a linear extension of addressable memory space of a microprocessor with minimal additional hardware and software complexity. A N+x bit pointer register (e.g. program counter) holds an N+x bit instruction address. The N+x bit instruction address provides to an execution unit a pointer to an instruction in the memory to be processed by the execution unit. An encoder encodes the N+x bit address into an N bit encoding of the N+x bit address. The processor core can thereby address 2.sup.x times more memory locations than 2.sup.N. Two other registers each hold a portion of a data address (i.e. a pointer to a datum in memory to be operated on). An address former concatenates the portions of the address in the two registers to form the data address. Therefore, the address is formed from portions of the data address stored in multiple registers without performing any arithmetic on the portions.

摘要翻译： 一种处理器内核，用于以最小的附加硬件和软件复杂性提供微处理器的可寻址存储空间的线性扩展。 N + x位指针寄存器（例如程序计数器）保存N + x位指令地址。 N + x位指令地址向执行单元提供指向由执行单元处理的存储器中的指令的指针。 编码器将N + x位地址编码为N + x位地址的N位编码。 因此，处理器核可以处理比2N多两倍的存储单元。 另外两个寄存器分别保存数据地址的一部分（即指向要操作的存储器中的基准的指针）。 地址前缀将两个寄存器中地址的部分连接起来形成数据地址。 因此，地址由存储在多个寄存器中的数据地址的部分形成，而不对这些部分执行任何算术。

公开(公告)号：US5822779A

公开(公告)日：1998-10-13

申请号：US821416

申请日：1997-03-21

申请人： Gideon Intrater ,  Ohad Falik ,  Aharon Ostrer ,  Yair Baydatch ,  Alberto Sandbank

发明人： Gideon Intrater ,  Ohad Falik ,  Aharon Ostrer ,  Yair Baydatch ,  Alberto Sandbank

IPC分类号： G06F13/42 ,  G06F15/78 ,  G06F13/18

CPC分类号： G06F13/4243 ,  G06F15/786

摘要： A data processing technique with which a CPU core accesses memory devices over a bus. Some of the memory devices are on-chip, and some may be off-chip. In order to optimize its operation, the CPU core accesses the on-chip devices via a core buffer interface unit ("BIU") which has been tuned to on-chip operation. Off-chip devices communicate with the CPU core via a system BIU which translates the on-chip bus transactions to meet the off-chip device requirements.

摘要翻译： 一种CPU核心通过总线访问存储器件的数据处理技术。 一些存储器件是芯片上的，一些存储器件可能是片外的。 为了优化其运行，CPU内核通过芯片缓冲接口单元（“BIU”）访问片上设备，该单元已被调谐到片上操作。 片外设备通过系统BIU与CPU内核进行通信，该系统转换片上总线事务以满足片外设备要求。

公开(公告)号：US5649208A

公开(公告)日：1997-07-15

申请号：US553012

申请日：1995-11-03

申请人： Gideon Intrater ,  Oved Oz ,  Meir Tsadik

发明人： Gideon Intrater ,  Oved Oz ,  Meir Tsadik

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F11/36 ,  G06F13/24 ,  G06F15/78 ,  H04L27/38 ,  G06F9/46

CPC分类号： G06F11/3648 ,  G06F11/3656 ,  G06F11/3664 ,  G06F13/24 ,  G06F15/7842 ,  G06F9/30167 ,  G06F9/32 ,  G06F9/3879 ,  H04L27/38

摘要： The central processing unit of an integrated circuit data processing system includes both means for processing a first non-maskable interrupt (NMI) request received by the data processing system on a first NMI request line and means for processing a second NMI request received by the data processing system on a second NMI request line different from the first NMI request line and within a predefined time period after receipt of the first NMI request. Both. NMI requests are serviced by the data processing system even if the second NMI request is received prior to completion of processing of the first request.

摘要翻译： 集成电路数据处理系统的中央处理单元包括用于处理由数据处理系统在第一NMI请求线上接收的第一不可屏蔽中断（NMI）请求的装置和用于处理由数据接收的第二NMI请求的装置的装置 处理系统在与第一NMI请求行不同的第二NMI请求行上并且在接收到第一NMI请求之后的预定时间段内。 都。 即使在完成第一个请求的处理之前接收到第二个NMI请求，NMI请求也由数据处理系统服务。