公开(公告)号：US06800517B2

公开(公告)日：2004-10-05

申请号：US10792532

申请日：2004-03-02

申请人： Gurtej S. Sandhu ,  Trung Tri Doan ,  Howard E. Rhodes ,  Sujit Sharan ,  Philip J. Ireland ,  Martin Ceredig Roberts

发明人： Gurtej S. Sandhu ,  Trung Tri Doan ,  Howard E. Rhodes ,  Sujit Sharan ,  Philip J. Ireland ,  Martin Ceredig Roberts

IPC分类号： H01L218238

CPC分类号： H01L21/76877 ,  H01L21/28518

摘要： The invention includes a method of forming a conductive interconnect. An electrical node location is defined to be supported by a silicon-containing substrate. A silicide is formed in contact with the electrical node location. The silicide is formed by exposing the substrate to hydrogen, TiCl4 and plasma conditions to cause Ti from the TiCl4 to combine with silicon of the substrate to form TiSix. Conductively doped silicon material is formed over the silicide. The conductively doped silicon material is exposed to one or more temperatures of at least about 800° C. The silicide is also exposed to the temperatures of at least about 800° C.

公开(公告)号：US06750089B2

公开(公告)日：2004-06-15

申请号：US10355538

申请日：2003-01-30

申请人： Gurtej S. Sandhu ,  Trung Tri Doan ,  Howard E. Rhodes ,  Sujit Sharan ,  Philip J. Ireland ,  Martin Ceredig Roberts

发明人： Gurtej S. Sandhu ,  Trung Tri Doan ,  Howard E. Rhodes ,  Sujit Sharan ,  Philip J. Ireland ,  Martin Ceredig Roberts

IPC分类号： H01L218238

CPC分类号： H01L21/76877 ,  H01L21/28518

摘要： The invention includes a method of forming a conductive interconnect. An electrical node location is defined to be supported by a silicon-containing substrate. A silicide is formed in contact with the electrical node location. The silicide is formed by exposing the substrate to hydrogen, TiCl4 and plasma conditions to cause Ti from the TiCl4 to combine with silicon of the substrate to form TiSix. Conductively doped silicon material is formed over the silicide. The conductively doped silicon material is exposed to one or more temperatures of at least about 800° C. The silicide is also exposed to the temperatures of at least about 800° C.

摘要翻译： 本发明包括形成导电互连的方法。 电节点位置被定义为由含硅衬底支撑。 形成与电节点位置接触的硅化物。 硅化物通过将衬底暴露于氢气，TiCl 4和等离子体条件来形成，以使来自TiCl 4的Ti与衬底的硅结合形成TiSix。 在硅化物上形成导电掺杂的硅材料。 导电掺杂的硅材料暴露于至少约800℃的一个或多个温度。硅化物还暴露于至少约800℃的温度

公开(公告)号：US06531352B1

公开(公告)日：2003-03-11

申请号：US09653151

申请日：2000-08-31

申请人： Gurtej S. Sandhu ,  Trung Tri Doan ,  Howard E. Rhodes ,  Sujit Sharan ,  Philip J. Ireland ,  Martin Ceredig Roberts

发明人： Gurtej S. Sandhu ,  Trung Tri Doan ,  Howard E. Rhodes ,  Sujit Sharan ,  Philip J. Ireland ,  Martin Ceredig Roberts

IPC分类号： H01L218238

CPC分类号： H01L21/76877 ,  H01L21/28518

摘要： The invention includes a method of forming a conductive interconnect. An electrical node location is defined to be supported by a silicon-containing substrate. A silicide is formed in contact with the electrical node location. The silicide is formed by exposing the substrate to hydrogen, TiCl4 and plasma conditions to cause Ti from the TiCl4 to combine with silicon of the substrate to form TiSix. Conductively doped silicon material is formed over the silicide. The conductively doped silicon material is exposed to one or more temperatures of at least about 800° C. The silicide is also exposed to the temperatures of at least about 800° C.

公开(公告)号：US07368372B2

公开(公告)日：2008-05-06

申请号：US11386167

申请日：2006-03-21

申请人： Fred D. Fishburn ,  Martin Ceredig Roberts

发明人： Fred D. Fishburn ,  Martin Ceredig Roberts

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/8236

CPC分类号： H01L21/31053 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823828 ,  H01L21/823842 ,  Y10S438/941

摘要： The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, the insulative capping layer, and the conductive gate layer are patterned and etched to form a first set of conductive gate constructions over the substrate. A dielectric material is formed and planarized over the first set of gate constructions. Thereafter, the insulative capping layer and the conductive gate layer are patterned and etched to form a second set of conductive gate constructions over the substrate. Other aspects and implementations are contemplated.

摘要翻译： 本发明包括制造多组场效应晶体管的方法。 在一个实施方案中，在绝缘覆盖层上形成蚀刻停止层，所述绝缘覆盖层形成在形成在衬底上的导电栅极层上。 蚀刻停止层，绝缘覆盖层和导电栅极层被图案化和蚀刻以在衬底上形成第一组导电栅极结构。 在第一组栅极结构上形成并平坦化介电材料。 此后，对绝缘覆盖层和导电栅极层进行构图和蚀刻，以在衬底上形成第二组导电栅极结构。 考虑了其他方面和实现。

公开(公告)号：US07060570B2

公开(公告)日：2006-06-13

申请号：US10914825

申请日：2004-08-09

申请人： Fred D. Fishburn ,  Martin Ceredig Roberts

发明人： Fred D. Fishburn ,  Martin Ceredig Roberts

IPC分类号： H01L21/8232

CPC分类号： H01L21/31053 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823828 ,  H01L21/823842 ,  Y10S438/941

摘要： The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, the insulative capping layer, and the conductive gate layer are patterned and etched to form a first set of conductive gate constructions over the substrate. A dielectric material is formed and planarized over the first set of gate constructions. Thereafter, the insulative capping layer and the conductive gate layer are patterned and etched to form a second set of conductive gate constructions over the substrate. Other aspects and implementations are contemplated.

公开(公告)号：US06717201B2

公开(公告)日：2004-04-06

申请号：US09198034

申请日：1998-11-23

申请人： Martin Ceredig Roberts ,  Christophe Pierrat

发明人： Martin Ceredig Roberts ,  Christophe Pierrat

IPC分类号： H01L27108

CPC分类号： H01L27/10855 ,  H01L28/91

摘要： Capacitors, DRAM circuitry, and methods of forming the same are described. In one embodiment, a capacitor comprises a first container which is joined with a substrate node location and has an opening defining a first interior area. A second container is joined with the node location and has an opening defining a second interior area. The areas are spaced apart from one another in a non-overlapping relationship. A dielectric layer and a conductive capacitor electrode layer are disposed operably proximate the first and second containers. In another embodiment, the first and second containers are generally elongate and extend away from the node location along respective first and second central axes. The axes are different and spaced apart from one another. In yet another embodiment, a conductive layer of material is disposed over and in electrical communication with a substrate node location. The layer of material has an outer surface with a first region and a second region spaced apart from the first region. A first container is formed over and in electrical communication with the first region and a second container is formed over and in electrical communication with the second region. In yet another embodiment, the first and second containers define container volumes which are discrete and separated from one another.

摘要翻译： 描述了电容器，DRAM电路及其形成方法。 在一个实施例中，电容器包括与衬底节点位置连接并具有限定第一内部区域的开口的第一容器。 第二容器与节点位置连接并且具有限定第二内部区域的开口。 这些区域以不重叠的关系彼此间隔开。 电介质层和导电电容器电极层可操作地设置在第一和第二容器的附近。 在另一个实施例中，第一和第二容器通常是细长的并且沿相应的第一和第二中心轴线远离节点位置延伸。 轴是不同的并且彼此间隔开。 在另一个实施例中，材料的导电层设置在衬底节点位置上并与衬底节点位置电连通。 材料层具有外表面，其具有第一区域和与第一区域间隔开的第二区域。 第一容器形成在第一区域之上并与第一区域电连通，并且第二容器形成在第二区域上并与第二区域电连通。 在另一个实施例中，第一和第二容器限定彼此离散和分离的容器体积。

公开(公告)号：US06475850B2

公开(公告)日：2002-11-05

申请号：US09873808

申请日：2001-06-04

申请人： Michael Violette ,  Martin Ceredig Roberts

发明人： Michael Violette ,  Martin Ceredig Roberts

IPC分类号： H01L218238

CPC分类号： H01L21/8249

摘要： A BiCMOS integrated circuit is fabricated using a minimum number of wafer processing steps and yet offers the IC circuit designer five (5) different transistor types. These types include P-channel and N-channel MOS transistors and three different bipolar transistors whose emitters are all formed by a different process and all are characterized by different current gains and different breakdown voltages. A differential silicon dioxide/silicon nitride masking technique is used in the IC fabrication process wherein both P-type buried layers (PBL) and N-type buried layers (NBL) are formed in a silicon substrate using a single mask set and further wherein P-type wells and N-type wells are formed above these buried layers in an epitaxial layer, also using a single SiO2/Si3N4 differential mask set. Two of the bipolar transistor emitters are formed by out diffusion from first and second levels of polysilicon, whereas the emitter of the third bipolar transistor is formed by ion implantation doping.

摘要翻译： 使用最少数量的晶圆处理步骤制造BiCMOS集成电路，并提供IC电路设计器五（5）种不同的晶体管类型。 这些类型包括P沟道和N沟道MOS晶体管以及三个不同的双极晶体管，其发射极都由不同的工艺形成，并且都以不同的电流增益和不同的击穿电压为特征。 在IC制造工艺中使用差示二氧化硅/氮化硅掩蔽技术，其中使用单个掩模组在硅衬底中形成P型掩埋层（PBL）和N型掩埋层（NBL），并且其中P 类型的阱和N型阱在外延层上形成在这些掩埋层上方，也使用单个SiO 2 / Si 3 N 4差分掩模集合。 两个双极晶体管发射极通过从第一和第二层多晶硅的扩散形成，而第三双极晶体管的发射极通过离子注入掺杂形成。

公开(公告)号：US06221711B1

公开(公告)日：2001-04-24

申请号：US09076324

申请日：1998-05-11

申请人： Martin Ceredig Roberts ,  Kunal R. Parekh

发明人： Martin Ceredig Roberts ,  Kunal R. Parekh

IPC分类号： H01L218242

CPC分类号： H01L21/76838 ,  H01L21/768 ,  H01L21/76802 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry are described. In one embodiment, a pair of conductive contact plugs are formed to project outwardly relative to a semiconductor wafer. The plugs have respective tops, one of which being covered with different first and second insulating materials. An opening is etched through one of the first and second insulating materials to expose only one of the tops of the pair of plugs. Electrically conductive material is formed within the opening and in electrical connection with the one plug. In a preferred embodiment, two-spaced apart conductive lines are formed over a substrate and conductive plugs are formed between, and on each side of the conductive lines. The conductive plug formed between the conductive lines provides a bit line contact plug having an at least partially exposed top portion. The exposed top portion is encapsulated with a first insulating material. A layer of second different insulating material is formed over the substrate. Portions of the second insulating material are removed selectively relative to the first insulating material over the conductive plugs on each side of the conductive lines to provide a pair of capacitor containers. Capacitors are subsequently formed in the containers.

摘要翻译： 描述了与导电插塞电接触的方法，形成接触开口的方法以及形成动态随机存取存储器电路的方法。 在一个实施例中，形成一对导电接触插塞相对于半导体晶片向外突出。 插头具有相应的顶部，其中一个顶部覆盖有不同的第一和第二绝缘材料。 通过第一绝缘材料和第二绝缘材料之一蚀刻开口以露出该对插头的顶部中的一个。 导电材料形成在开口内并与一个插头电连接。 在优选实施例中，在衬底上形成两个间隔开的导电线，并且在导电线的每一侧之间和之间形成导电插塞。 形成在导电线之间的导电插塞提供具有至少部分暴露的顶部的位线接触插头。 暴露的顶部用第一绝缘材料封装。 在衬底上形成第二不同绝缘材料层。 通过在导电线的每一侧上的导电插塞上相对于第一绝缘材料选择性地去除第二绝缘材料的部分，以提供一对电容器容器。 随后在容器中形成电容器。

公开(公告)号：US07071058B2

公开(公告)日：2006-07-04

申请号：US10817548

申请日：2004-04-02

申请人： Martin Ceredig Roberts ,  Christophe Pierrat

发明人： Martin Ceredig Roberts ,  Christophe Pierrat

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L27/10855 ,  H01L28/91

摘要： Capacitors, DRAM circuitry, and methods of forming the same are described. In one embodiment, a capacitor comprises a first container which is joined with a substrate node location and has an opening defining a first interior area. A second container is joined with the node location and has an opening defining a second interior area. The areas are spaced apart from one another in a non-overlapping relationship. A dielectric layer and a conductive capacitor electrode layer are disposed operably proximate the first and second containers. In another embodiment, the first and second containers are generally elongate and extend away from the node location along respective first and second central axes. The axes are different and spaced apart from one another. In yet another embodiment, a conductive layer of material is disposed over and in electrical communication with a substrate node location. The layer of material has an outer surface with a first region and a second region spaced apart from the first region. A first container is formed over and in electrical communication with the first region and a second container is formed over and in electrical communication with the second region. In yet another embodiment, the first and second containers define container volumes which are discrete and separated from one another.

摘要翻译： 描述了电容器，DRAM电路及其形成方法。 在一个实施例中，电容器包括与衬底节点位置连接并具有限定第一内部区域的开口的第一容器。 第二容器与节点位置连接并且具有限定第二内部区域的开口。 这些区域以不重叠的关系彼此间隔开。 电介质层和导电电容器电极层可操作地设置在第一和第二容器的附近。 在另一个实施例中，第一和第二容器通常是细长的并且沿相应的第一和第二中心轴线远离节点位置延伸。 轴是不同的并且彼此间隔开。 在另一个实施例中，材料的导电层设置在衬底节点位置上并与衬底节点位置电连通。 材料层具有外表面，其具有第一区域和与第一区域间隔开的第二区域。 第一容器形成在第一区域之上并与第一区域电连通，并且第二容器形成在第二区域上并与第二区域电连通。 在另一个实施例中，第一和第二容器限定彼此离散和分离的容器体积。

公开(公告)号：US06727139B2

公开(公告)日：2004-04-27

申请号：US10273881

申请日：2002-10-17

申请人： Martin Ceredig Roberts ,  Kunal R. Parekh

发明人： Martin Ceredig Roberts ,  Kunal R. Parekh

IPC分类号： H01L218242

CPC分类号： H01L21/76838 ,  H01L21/768 ,  H01L21/76802 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry are described. In one embodiment, a pair of conductive contact plugs are formed to project outwardly relative to a semiconductor wafer. The plugs have respective tops, one of which being covered with different first and second insulating materials. An opening is etched through one of the first and second insulating materials to expose only one of the tops of the pair of plugs. Electrically conductive material is formed within the opening and in electrical connection with the one plug. In a preferred embodiment, two-spaced apart conductive lines are formed over a substrate and conductive plugs are formed between, and on each side of the conductive lines. The conductive plug formed between the conductive lines provides a bit line contact plug having an at least partially exposed top portion. The exposed top portion is encapsulated with a first insulating material. A layer of second different insulating material is formed over the substrate. Portions of the second insulating material are removed selectively relative to the first insulating material over the conductive plugs on each side of the conductive lines to provide a pair of capacitor containers. Capacitors are subsequently formed in the containers.

摘要翻译： 描述了与导电插塞电接触的方法，形成接触开口的方法以及形成动态随机存取存储器电路的方法。 在一个实施例中，形成一对导电接触插塞相对于半导体晶片向外突出。 插头具有相应的顶部，其中一个顶部覆盖有不同的第一和第二绝缘材料。 通过第一绝缘材料和第二绝缘材料之一蚀刻开口以露出该对插头的顶部中的一个。 导电材料形成在开口内并与一个插头电连接。 在优选实施例中，在衬底上形成两个间隔开的导电线，并且在导电线的每一侧之间和之间形成导电插塞。 形成在导电线之间的导电插塞提供具有至少部分暴露的顶部的位线接触插头。 暴露的顶部用第一绝缘材料封装。 在衬底上形成第二不同绝缘材料层。 通过在导电线的每一侧上的导电插塞上相对于第一绝缘材料选择性地去除第二绝缘材料的部分，以提供一对电容器容器。 随后在容器中形成电容器。