公开(公告)号：US06221711B1

公开(公告)日：2001-04-24

申请号：US09076324

申请日：1998-05-11

申请人： Martin Ceredig Roberts ,  Kunal R. Parekh

发明人： Martin Ceredig Roberts ,  Kunal R. Parekh

IPC分类号： H01L218242

CPC分类号： H01L21/76838 ,  H01L21/768 ,  H01L21/76802 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry are described. In one embodiment, a pair of conductive contact plugs are formed to project outwardly relative to a semiconductor wafer. The plugs have respective tops, one of which being covered with different first and second insulating materials. An opening is etched through one of the first and second insulating materials to expose only one of the tops of the pair of plugs. Electrically conductive material is formed within the opening and in electrical connection with the one plug. In a preferred embodiment, two-spaced apart conductive lines are formed over a substrate and conductive plugs are formed between, and on each side of the conductive lines. The conductive plug formed between the conductive lines provides a bit line contact plug having an at least partially exposed top portion. The exposed top portion is encapsulated with a first insulating material. A layer of second different insulating material is formed over the substrate. Portions of the second insulating material are removed selectively relative to the first insulating material over the conductive plugs on each side of the conductive lines to provide a pair of capacitor containers. Capacitors are subsequently formed in the containers.

摘要翻译： 描述了与导电插塞电接触的方法，形成接触开口的方法以及形成动态随机存取存储器电路的方法。 在一个实施例中，形成一对导电接触插塞相对于半导体晶片向外突出。 插头具有相应的顶部，其中一个顶部覆盖有不同的第一和第二绝缘材料。 通过第一绝缘材料和第二绝缘材料之一蚀刻开口以露出该对插头的顶部中的一个。 导电材料形成在开口内并与一个插头电连接。 在优选实施例中，在衬底上形成两个间隔开的导电线，并且在导电线的每一侧之间和之间形成导电插塞。 形成在导电线之间的导电插塞提供具有至少部分暴露的顶部的位线接触插头。 暴露的顶部用第一绝缘材料封装。 在衬底上形成第二不同绝缘材料层。 通过在导电线的每一侧上的导电插塞上相对于第一绝缘材料选择性地去除第二绝缘材料的部分，以提供一对电容器容器。 随后在容器中形成电容器。

公开(公告)号：US06727139B2

公开(公告)日：2004-04-27

申请号：US10273881

申请日：2002-10-17

申请人： Martin Ceredig Roberts ,  Kunal R. Parekh

发明人： Martin Ceredig Roberts ,  Kunal R. Parekh

IPC分类号： H01L218242

CPC分类号： H01L21/76838 ,  H01L21/768 ,  H01L21/76802 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry are described. In one embodiment, a pair of conductive contact plugs are formed to project outwardly relative to a semiconductor wafer. The plugs have respective tops, one of which being covered with different first and second insulating materials. An opening is etched through one of the first and second insulating materials to expose only one of the tops of the pair of plugs. Electrically conductive material is formed within the opening and in electrical connection with the one plug. In a preferred embodiment, two-spaced apart conductive lines are formed over a substrate and conductive plugs are formed between, and on each side of the conductive lines. The conductive plug formed between the conductive lines provides a bit line contact plug having an at least partially exposed top portion. The exposed top portion is encapsulated with a first insulating material. A layer of second different insulating material is formed over the substrate. Portions of the second insulating material are removed selectively relative to the first insulating material over the conductive plugs on each side of the conductive lines to provide a pair of capacitor containers. Capacitors are subsequently formed in the containers.

摘要翻译： 描述了与导电插塞电接触的方法，形成接触开口的方法以及形成动态随机存取存储器电路的方法。 在一个实施例中，形成一对导电接触插塞相对于半导体晶片向外突出。 插头具有相应的顶部，其中一个顶部覆盖有不同的第一和第二绝缘材料。 通过第一绝缘材料和第二绝缘材料之一蚀刻开口以露出该对插头的顶部中的一个。 导电材料形成在开口内并与一个插头电连接。 在优选实施例中，在衬底上形成两个间隔开的导电线，并且在导电线的每一侧之间和之间形成导电插塞。 形成在导电线之间的导电插塞提供具有至少部分暴露的顶部的位线接触插头。 暴露的顶部用第一绝缘材料封装。 在衬底上形成第二不同绝缘材料层。 通过在导电线的每一侧上的导电插塞上相对于第一绝缘材料选择性地去除第二绝缘材料的部分，以提供一对电容器容器。 随后在容器中形成电容器。

公开(公告)号：US06486018B2

公开(公告)日：2002-11-26

申请号：US09791229

申请日：2001-02-22

申请人： Martin Ceredig Roberts ,  Kunal R. Parekh

发明人： Martin Ceredig Roberts ,  Kunal R. Parekh

IPC分类号： H01L218242

CPC分类号： H01L21/76838 ,  H01L21/768 ,  H01L21/76802 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry are described. In one embodiment, a pair of conductive contact plugs are formed to project outwardly relative to a semiconductor wafer. The plugs have respective tops, one of which being covered with different first and second insulating materials. An opening is etched through one of the first and second insulating materials to expose only one of the tops of the pair of plugs. Electrically conductive material is formed within the opening and in electrical connection with the one plug. In a preferred embodiment, two-spaced apart conductive lines are formed over a substrate and conductive plugs are formed between, and on each side of the conductive lines. The conductive plug formed between the conductive lines provides a bit line contact plug having an at least partially exposed top portion. The exposed top portion is encapsulated with a first insulating material. A layer of second different insulating material is formed over the substrate. Portions of the second insulating material are removed selectively relative to the first insulating material over the conductive plugs on each side of the conductive lines to provide a pair of capacitor containers. Capacitors are subsequently formed in the containers.

摘要翻译： 描述了与导电插塞电接触的方法，形成接触开口的方法以及形成动态随机存取存储器电路的方法。 在一个实施例中，形成一对导电接触插塞相对于半导体晶片向外突出。 插头具有相应的顶部，其中一个顶部覆盖有不同的第一和第二绝缘材料。 通过第一绝缘材料和第二绝缘材料之一蚀刻开口以露出该对插头的顶部中的一个。 导电材料形成在开口内并与一个插头电连接。 在优选实施例中，在衬底上形成两个间隔开的导电线，并且在导电线的每一侧之间和之间形成导电插塞。 形成在导电线之间的导电插塞提供具有至少部分暴露的顶部的位线接触插头。 暴露的顶部用第一绝缘材料封装。 在衬底上形成第二不同绝缘材料层。 通过在导电线的每一侧上的导电插塞上相对于第一绝缘材料选择性地去除第二绝缘材料的部分，以提供一对电容器容器。 随后在容器中形成电容器。

公开(公告)号：US09343665B2

公开(公告)日：2016-05-17

申请号：US12166604

申请日：2008-07-02

申请人： Nishant Sinha ,  John Smythe ,  Bhaskar Srinivasan ,  Gurtej S. Sandhu ,  Joseph Neil Greeley ,  Kunal R. Parekh

发明人： Nishant Sinha ,  John Smythe ,  Bhaskar Srinivasan ,  Gurtej S. Sandhu ,  Joseph Neil Greeley ,  Kunal R. Parekh

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/1683 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

摘要： A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated.

摘要翻译： 形成非易失性电阻氧化物存储单元的方法包括：形成存储单元的第一导电电极作为衬底的一部分。 含金属氧化物的材料形成在第一导电电极上。 蚀刻停止材料沉积在包含金属氧化物的材料上。 导电材料沉积在蚀刻停止材料上。 包含所接收的导电材料的存储单元的第二导电电极形成在蚀刻停止材料上。 这样包括通过导电材料蚀刻以相对于蚀刻停止材料停止并且形成非易失性电阻氧化物存储单元，以包括具有包含金属氧化物的材料和其间的蚀刻停止材料的第一和第二导电电极。 考虑其他实现。

公开(公告)号：US08404587B2

公开(公告)日：2013-03-26

申请号：US13160363

申请日：2011-06-14

申请人： Kyle K. Kirby ,  Kunal R. Parekh

发明人： Kyle K. Kirby ,  Kunal R. Parekh

IPC分类号： H01L21/44

CPC分类号： H01L21/743 ,  H01L21/26513 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/49816 ,  H01L27/0694 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/66568 ,  H01L29/78 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548

摘要： Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

公开(公告)号：US20110193226A1

公开(公告)日：2011-08-11

申请号：US12701800

申请日：2010-02-08

申请人： Kyle K. Kirby ,  Kunal R. Parekh ,  Sarah A. Niroumand

发明人： Kyle K. Kirby ,  Kunal R. Parekh ,  Sarah A. Niroumand

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/488

CPC分类号： H01L21/76877 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/76805 ,  H01L21/76883 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/06 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05552

摘要： Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.

摘要翻译： 本文公开了具有贯穿衬底互连和相关制造方法的微电子器件。 在一个实施例中，半导体器件包括承载第一和第二金属化层的半导体衬底。 第二金属化层与半导体衬底间隔开，其间具有第一金属化层。 半导体器件还包括至少部分延伸穿过半导体衬底的导电互连。 第一金属化层经由第二金属化层与导电互连电接触。

公开(公告)号：US07902028B2

公开(公告)日：2011-03-08

申请号：US12724589

申请日：2010-03-16

申请人： Young Pil Kim ,  Kunal R. Parekh

发明人： Young Pil Kim ,  Kunal R. Parekh

IPC分类号： H01L21/336

CPC分类号： H01L21/823462 ,  H01L21/823456 ,  H01L21/823487 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621

摘要： The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates. In one implementation, a method of forming a field effect transistor includes forming masking material over semiconductive material of a substrate. A trench is formed through the masking material and into the semiconductive material. Gate dielectric material is formed within the trench in the semiconductive material. Gate material is deposited within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material. Source/drain regions are formed. Other aspects and implementations are contemplated.

摘要翻译： 本发明包括形成场效应晶体管的方法，形成场效应晶体管栅极的方法，形成集成电路的方法，该集成电路包括晶体管门阵列和门阵列的外围电路，以及形成集成电路的方法，该集成电路包括晶体管门阵列，其包括第一栅极 和第二接地隔离门。 在一个实施方案中，形成场效应晶体管的方法包括在衬底的半导体材料上形成掩模材料。 通过掩模材料形成沟槽并进入半导体材料。 栅介电材料形成在半导体材料的沟槽内。 栅极材料沉积在掩模材料中的沟槽内并且在半导体材料中的沟槽内沉积在栅极电介质材料上。 形成源/漏区。 考虑了其他方面和实现。

公开(公告)号：US20100295109A1

公开(公告)日：2010-11-25

申请号：US12852169

申请日：2010-08-06

申请人： Kunal R. Parekh

发明人： Kunal R. Parekh

IPC分类号： H01L27/108

CPC分类号： H01L29/78 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10805 ,  H01L27/10873 ,  H01L27/1207 ,  H01L29/0603 ,  H01L29/7841

摘要： Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.

摘要翻译： 一些实施例包括具有在SOI上部分延伸的晶体管栅极的DRAM以及形成这种DRAM的方法。 DRAM的单位单元可以在有源区域基座内，并且在一些实施例中，单位单元可以包括具有与有源区域基座的侧壁直接接触的存储节点的电容器。 一些实施例包括具有完全在SOI上的晶体管栅极的OC1T存储器，以及形成这种0C1T存储器的方法。

公开(公告)号：US07833892B2

公开(公告)日：2010-11-16

申请号：US11704488

申请日：2007-02-09

申请人： Kunal R. Parekh ,  John K. Zahurak

发明人： Kunal R. Parekh ,  John K. Zahurak

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/336

CPC分类号： H01L21/823468 ,  H01L21/823418 ,  H01L21/823425 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11534

摘要： The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain region and which is spaced from an anisotropically etched sidewall spacer proximate a gate of the transistor.

摘要翻译： 本发明包括形成集成电路的方法，形成存储器电路的方法以及形成场效应晶体管的方法。 在一个实施方案中，导电金属硅化物形成在衬底的一些区域上而不是其它区域上。 在一个实施方案中，导电金属硅化物形成在晶体管源极/漏极区上，并且与靠近晶体管的栅极的各向异性蚀刻的侧壁间隔开。

公开(公告)号：US20100133612A1

公开(公告)日：2010-06-03

申请号：US12697991

申请日：2010-02-01

申请人： Gurtej S. Sandhu ,  Kunal R. Parekh

发明人： Gurtej S. Sandhu ,  Kunal R. Parekh

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/28

CPC分类号： H01L29/4983 ,  H01L21/28114 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7843 ,  H01L29/7845 ,  Y10S257/90

摘要： The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain can be obtained through non symmetric placement of stress inducing structures as part of the gate electrode.

摘要翻译： 在集成电路中使用应变栅电极导致晶体管具有改善的载流子迁移率，改进的驱动特性和减少的源极漏极结泄漏。 栅电极应变可以通过不对称放置应力诱导结构作为栅电极的一部分获得。