公开(公告)号：US06393528B1

公开(公告)日：2002-05-21

申请号：US09345714

申请日：1999-06-30

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  James Stephen Fields, Jr.

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  James Stephen Fields, Jr.

IPC分类号： G06F1200

CPC分类号： G06F12/0862 ,  G06F12/127

摘要： A method of operating a computer system is disclosed in which an instruction having an explicit prefetch request is issued directly from an instruction sequence unit to a prefetch unit of a processing unit. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster). If another prefetch value is requested from the memory hiearchy and it is determined that a prefetch limit of cache usage has been met by the cache, then a cache line in the cache containing one of the earlier prefetch values is allocated for receiving the other prefetch value.

摘要翻译： 公开了一种操作计算机系统的方法，其中具有显式预取请求的指令直接从指令序列单元发送到处理单元的预取单元。 在优选实施例中，使用两个预取单元，第一预取单元是硬件独立的，并且动态地监视与由处理单元的核心执行的操作相关联的一个或多个活动流，并且第二预取单元知道较低级别 存储子系统，并用预取请求发送将预取值加载到处理单元的较低级缓存中的指示。 本发明可以有利地将每个预取请求与相关联的处理器流的流ID或请求处理单元的处理器ID相关联（后一特征对于由处理单元簇共享的高速缓存特别有用）。 如果从存储器hiearchy请求另一个预取值，并且确定高速缓存的高速缓存使用的预取限制已被满足，则包含先前预取值中的一个的高速缓存行中的高速缓存行被分配用于接收另一个预取值 。

公开(公告)号：US06581139B1

公开(公告)日：2003-06-17

申请号：US09339411

申请日：1999-06-24

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie

IPC分类号： G06F1200

CPC分类号： G06F12/0864

摘要： A set-associative cache memory having asymmetric latency among sets is disclosed. The cache memory has multiple congruence classes of cache lines. Each congruence class includes a number of sets organized in a set-associative manner. The cache memory further includes a means for accessing at least one of the sets faster than the remaining sets having an identical access latency.

摘要翻译： 公开了一组在集合中具有非对称等待时间的组合高速缓冲存储器。 高速缓存存储器具有多个一致的缓存行类。 每个同余类包括以组合方式组织的多个集合。 高速缓冲存储器还包括用于比具有相同访问延迟的其余集合更快地访问集合中的至少一个集合的装置。

公开(公告)号：US06510494B1

公开(公告)日：2003-01-21

申请号：US09345716

申请日：1999-06-30

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  James Stephen Fields, Jr.

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  James Stephen Fields, Jr.

IPC分类号： G06F1208

CPC分类号： G06F9/3802 ,  G06F9/383 ,  G06F12/0862 ,  G06F12/0897

摘要： A method of operating a processing unit of a computer system, by issuing an instruction having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the pref etch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit.

摘要翻译： 一种操作计算机系统的处理单元的方法，通过从指令序列单元向处理单元的预取单元发出具有显式预取请求的指令。 本发明适用于作为操作数数据或指令的值。 在优选实施例中，使用两个预取单元，第一预取单元是硬件独立的，并且动态地监视与由处理单元的核心执行的操作相关联的一个或多个活动流，并且第二预取单元知道较低级别 存储子系统，并用pref蚀刻请求发送将预取值加载到处理单元的较低级缓存中的指示。 本发明可以有利地将每个预取请求与相关联的处理器流的流ID或请求处理单元的处理器ID相关联。

公开(公告)号：US06460118B1

公开(公告)日：2002-10-01

申请号：US09339410

申请日：1999-06-24

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie

IPC分类号： C06F1200

CPC分类号： G06F12/0864 ,  G06F12/1054

摘要： A set-associative cache memory having incremental access latencies among sets is disclosed. The cache memory has multiple congruence classes of cache lines. Each congruence class includes a number of sets organized in a set-associative manner. In accordance with a preferred embodiment of the present invention, the cache memory further includes a means for accessing each of the sets with an access time dependent on a relative location of each of the sets such that access latency varies incrementally among sets.

摘要翻译： 公开了一种在集合中具有增量接入延迟的集合关联高速缓冲存储器。 高速缓存存储器具有多个一致的缓存行类。 每个同余类包括以组合方式组织的多个集合。 根据本发明的优选实施例，高速缓存存储器还包括用于以取决于每个集合的相对位置的访问时间来访问每个集合的装置，使得访问延迟在集合之间递增地变化。

公开(公告)号：US06460117B1

公开(公告)日：2002-10-01

申请号：US09339409

申请日：1999-06-24

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie

IPC分类号： G06F1200

CPC分类号： G06F12/0893 ,  G06F12/0864 ,  G06F12/123

摘要： A set-associative cache memory having a mechanism for migrating a most recently used set is disclosed. The cache memory has multiple congruence classes of cache lines. Each congruence class includes a number of sets organized in a set-associative manner. The cache memory further includes a migration means for directing the information from a cache “hit” to a predetermined set of the cache memory.

摘要翻译： 公开了具有用于迁移最近使用的集合的机制的集合关联缓存存储器。 高速缓存存储器具有多个一致的缓存行类。 每个同余类包括以组合方式组织的多个集合。 高速缓冲存储器还包括用于将信息从高速缓存“命中”引导到高速缓冲存储器的预定集合的迁移装置。

公开(公告)号：US06421763B1

公开(公告)日：2002-07-16

申请号：US09345642

申请日：1999-06-30

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  James Stephen Fields, Jr.

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  James Stephen Fields, Jr.

IPC分类号： G06F1208

CPC分类号： G06F12/0862 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3885 ,  G06F12/0897 ,  G06F2212/6028

摘要： A method of operating a processing unit of a computer system, by issuing an instruction having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster). If another prefetch value is requested from the memory hierarchy, and it is determined that a prefetch limit of cache usage has been met by the cache, then a cache line in the cache containing one of the earlier prefetch values is allocated for receiving the other prefetch value. The prefetch limit of cache usage may be established with a maximum number of sets in a congruence class usable by the requesting processing unit. A flag in a directory of the cache may be set to indicate that the prefetch value was retrieved as the result of a prefetch operation. In the implementation wherein the cache is a multi-level cache, a second flag in the cache directory may be set to indicate that the prefetch value has been sourced to an upstream cache. A cache line containing prefetch data can be automatically invalidated after a preset amount of time has passed since the prefetch value was requested.

摘要翻译： 一种操作计算机系统的处理单元的方法，通过从指令序列单元向处理单元的预取单元发出具有显式预取请求的指令。 本发明适用于作为操作数数据或指令的值。 在优选实施例中，使用两个预取单元，第一预取单元是硬件独立的，并且动态地监视与由处理单元的核心执行的操作相关联的一个或多个活动流，并且第二预取单元知道较低级别 存储子系统，并用预取请求发送将预取值加载到处理单元的较低级缓存中的指示。 本发明可以有利地将每个预取请求与相关联的处理器流的流ID或请求处理单元的处理器ID相关联（后一特征对于由处理单元簇共享的高速缓存特别有用）。 如果从存储器层次结构请求另一个预取值，并且确定高速缓存的高速缓存使用的预取限制已经被高速缓存满足，则分配包含较早预取值之一的高速缓存行中的高速缓存行用于接收另一个预取 值。 高速缓存使用的预取限制可以由请求处理单元可用的同余类中的最大数量的集合来建立。 高速缓存目录中的标志可以被设置为指示作为预取操作的结果检索预取值。 在其中缓存是多级高速缓存的实现中，高速缓存目录中的第二标志可以被设置为指示预取值已经被提供给上游高速缓存。 包含预取数据的缓存行可以在从请求预取值开始经过预设的时间后自动失效。

公开(公告)号：US06470427B1

公开(公告)日：2002-10-22

申请号：US09436373

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie

IPC分类号： G06F1200

CPC分类号： G06F12/0862 ,  G06F2212/6028

摘要： A programmable agent and method for managing prefetch queues provide dynamically configurable handling of priorities in a prefetching subsystem for providing look-ahead memory loads in a computer system. When it's queues are at capacity an agent handling prefetches from memory either ignores new requests, forces the new requests to retry or cancels a pending request in order to perform the new request. The behavior can be adjusted under program control by programming a register, or the control may be coupled to a load pattern analyzer. In addition, the behavior with respect to new requests can be set to different types depending on a phase of a pending request.

摘要翻译： 用于管理预取队列的可编程代理和方法为预取子系统中的优先级提供动态可配置的处理，以在计算机系统中提供先行存储器负载。 当队列处理能力时，代理处理来自内存的预取将忽略新的请求，强制新的请求重试或取消挂起的请求，以执行新的请求。 通过对寄存器进行编程，可以在程序控制下调整行为，或者控制可以耦合到负载模式分析器。 此外，根据待处理请求的阶段，关于新请求的行为可以被设置为不同的类型。

公开(公告)号：US06360299B1

公开(公告)日：2002-03-19

申请号：US09345644

申请日：1999-06-30

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  James Stephen Fields, Jr.

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  James Stephen Fields, Jr.

IPC分类号： G06F1200

CPC分类号： G06F12/0862 ,  G06F12/121 ,  G06F2212/6028

摘要： A method of operating a computer system is disclosed in which an instruction having an explicit prefetch request is issued directly from an instruction sequence unit to a prefetch unit of a processing unit. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster). If another prefetch value is requested from the memory hierarchy, and it is determined that a prefetch limit of cache usage has been met by the cache, then a cache line in the cache containing one of the earlier prefetch values is allocated for receiving the other prefetch value.

摘要翻译： 公开了一种操作计算机系统的方法，其中具有显式预取请求的指令直接从指令序列单元发送到处理单元的预取单元。 在优选实施例中，使用两个预取单元，第一预取单元是硬件独立的，并且动态地监视与由处理单元的核心执行的操作相关联的一个或多个活动流，并且第二预取单元知道较低级别 存储子系统，并用预取请求发送将预取值加载到处理单元的较低级缓存中的指示。 本发明可以有利地将每个预取请求与相关联的处理器流的流ID或请求处理单元的处理器ID相关联（后一特征对于由处理单元簇共享的高速缓存特别有用）。 如果从存储器层次结构请求另一个预取值，并且确定高速缓存的高速缓存使用的预取限制已经被高速缓存满足，则分配包含较早预取值之一的高速缓存行中的高速缓存行用于接收另一个预取 值。

公开(公告)号：US06721853B2

公开(公告)日：2004-04-13

申请号：US09895232

申请日：2001-06-29

申请人： Guy Lynn Guthrie ,  Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  John Steven Dodson

发明人： Guy Lynn Guthrie ,  Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  John Steven Dodson

IPC分类号： G06F1208

CPC分类号： G06F12/0813

摘要： A cache controller for a processor in a remote node of a system bus in a multiway multiprocessor link sends out a cache deallocate address transaction (CDAT) for a given cache line when that cache line is flushed and information from memory in a home node is no longer deemed valid for that cache line of that remote node processor. A local snoop of that CDAT transaction is then performed as a background function by other processors in the same remote node. If the snoop results indicate that same information is valid in another cache, and that cache decides it better to keep it valid in that remote node, then the information remains there. If the snoop results indicate that the information is not valid among caches in that remote node, or will be flushed due to the CDAT, the system memory directory in the home node of the multiprocessor link is notified and changes state in response to this. The system has higher performance due to the cache line maintenance functions being performed in the background rather than based on mainstream demand.

摘要翻译： 用于多路多处理器链路中的系统总线的远程节点中的处理器的高速缓存控制器在刷新该高速缓存行并且来自主节点中的存储器的信息为否的时候发送用于给定高速缓存行的缓存解除分配地址事务（CDAT） 较长时间被认为对该远程节点处理器的该缓存行有效。 然后，该同一远程节点中的其他处理器将执行该CDAT事务的本地侦听作为后台功能。 如果窥探结果表明相同的信息在另一个缓存中有效，并且该缓存决定更好地将其保留在该远程节点中，则该信息将保留在该位置。 如果窥探结果表明信息在该远程节点的高速缓存中无效，或由于CDAT而被刷新，则通知多处理器链路的家庭节点中的系统内存目录并响应于此改变状态。 该系统具有更高的性能，因为高速缓存行维护功能在后台执行，而不是基于主流需求。

公开(公告)号：US06532521B1

公开(公告)日：2003-03-11

申请号：US09345715

申请日：1999-06-30

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  James Stephen Fields, Jr.

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Guy Lynn Guthrie ,  James Stephen Fields, Jr.

IPC分类号： G06F1200

CPC分类号： G06F9/3802 ,  G06F9/30047 ,  G06F9/383 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/123 ,  G06F12/127

摘要： A method of operating a processing unit of a computer system, by issuing an instruction having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster). If another prefetch value is requested from the memory hierarchy, and it is determined that a prefetch limit of cache usage has been met by the cache, then a cache line in the cache containing one of the earlier prefetch values is allocated for receiving the other prefetch value. The prefetch limit of cache usage may be established with a maximum number of sets in a congruence class usable by the requesting processing unit. A flag in a directory of the cache may be set to indicate that the prefetch value was retrieved as the result of a prefetch operation. In the implementation wherein the cache is a multi-level cache, a second flag in the cache directory may be set to indicate that prefetch value has been sourced to an upstream cache. A cache line containing prefetch data can be automatically invalidated after a preset amount of time has passed since the prefetch value was requested.

摘要翻译： 一种操作计算机系统的处理单元的方法，通过从指令序列单元向处理单元的预取单元发出具有显式预取请求的指令。 本发明适用于作为操作数数据或指令的值。 在优选实施例中，使用两个预取单元，第一预取单元是硬件独立的，并且动态地监视与由处理单元的核心执行的操作相关联的一个或多个活动流，并且第二预取单元知道较低级别 存储子系统，并用预取请求发送将预取值加载到处理单元的较低级缓存中的指示。 本发明可以有利地将每个预取请求与相关联的处理器流的流ID或请求处理单元的处理器ID相关联（后一特征对于由处理单元簇共享的高速缓存特别有用）。 如果从存储器层次结构请求另一个预取值，并且确定高速缓存的高速缓存使用的预取限制已经被高速缓存满足，则分配包含较早预取值之一的高速缓存行中的高速缓存行用于接收另一个预取 值。 高速缓存使用的预取限制可以由请求处理单元可用的同余类中的最大数量的集合来建立。 高速缓存目录中的标志可以被设置为指示作为预取操作的结果检索预取值。 在其中高速缓存是多级高速缓存的实现中，高速缓存目录中的第二标志可以被设置为指示预取值已经被提供给上游高速缓存。 包含预取数据的缓存行可以在从请求预取值开始经过预设的时间后自动失效。