Abstract:
A device for measuring voltage, including a voltage detecting portion for detecting a plurality of voltages and outputting a maximum voltage of the plurality of voltages, a voltage latching portion that receives a first output from the voltage detecting portion, and a voltage reading portion that receives a second output from the voltage latching portion. Another device for measuring voltage, including a supply voltage, a ground voltage, and first and second supply voltage measuring units connected in parallel to each other between the supply voltage and the ground voltage. A method for measuring voltage, including receiving a plurality of voltages, detecting a maximum voltage from the plurality of voltages, maintaining the detected maximum voltage, and outputting the maintained detected maximum voltage.
Abstract:
A device for measuring voltage, including a voltage detecting portion for detecting a plurality of voltages and outputting a maximum voltage of the plurality of voltages, a voltage latching portion that receives a first output from the voltage detecting portion, and a voltage reading portion that receives a second output from the voltage latching portion. Another device for measuring voltage, including a supply voltage, a ground voltage, and first and second supply voltage measuring units connected in parallel to each other between the supply voltage and the ground voltage. A method for measuring voltage, including receiving a plurality of voltages, detecting a maximum voltage from the plurality of voltages, maintaining the detected maximum voltage, and outputting the maintained detected maximum voltage.
Abstract:
A semiconductor memory device and related test method are disclosed. Test data is defined from a group of M test bits selected from either input data or corresponding output data. A parallel bit test is then conducted on the test data. The M test bits include N test bits, where N is less than M, selected on a bit by bit basis from the output data, and L test bits, where N+L=M, selected from the input data. The selection of input data may be made in accordance with a don't care case for selected test data.
Abstract translation:公开了一种半导体存储器件及相关测试方法。 测试数据由从输入数据或相应输出数据中选择的一组M个测试位定义。 然后对测试数据进行并行比特测试。 M个测试位包括N个测试位,其中N小于M,从输出数据逐位选择,以及从输入数据中选择的L个测试位,其中N + L = M。 可以根据所选择的测试数据的不关心情况来进行输入数据的选择。