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    MEMORY INTEGRITY MONITORING
    1.
    发明申请
    MEMORY INTEGRITY MONITORING 审中-公开

    公开(公告)号：US20180211064A1

    公开(公告)日：2018-07-26

    申请号：US15415450

    申请日：2017-01-25

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Geoffrey Ndu ,  Adrian Shaw ,  Brian Quentin Monahan

    IPC: G06F21/64 ,  H04L9/32 ,  G06F21/60

    CPC classification number: G06F21/64 ,  G06F21/602 ,  H04L9/0643 ,  H04L9/3236

    Abstract: In one example in accordance with the present disclosure, a system comprises a first memory module and a first memory integrity monitoring processor, embedded to the first memory module, to receive a second hash corresponding to a second memory module. The second hash includes a second sequence number for reconstruction of a final hash value and the second hash is not sequentially a first number in a sequence for reconstruction of the final hash value. The first processor may receive a third hash corresponding to a third memory module. The third hash includes a third sequence number for reconstruction of the final hash value and the third hash is received after the second hash. The first processor may determine if the second hash can be combined with the third hash, combine the second hash and third hash into a partial hash reconstruct the final hash value using the partial hash.

    DATA TYPE MANAGEMENT
    2.
    发明申请
    DATA TYPE MANAGEMENT 审中-公开

    公开(公告)号：US20180150405A1

    公开(公告)日：2018-05-31

    申请号：US15577846

    申请日：2015-12-18

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Patrick Goldsack ,  Brian Quentin Monahan ,  James Salter ,  Adrian John Baldwin

    IPC: G06F12/1018 ,  G06F3/06

    CPC classification number: G06F12/1018 ,  G06F3/0619 ,  G06F3/0649 ,  G06F3/065 ,  G06F3/0679 ,  G06F8/437 ,  G06F2212/401

    Abstract: In one example in accordance with the present disclosure, a method for data type management may include adding a first data to a first data set. The first data set may belong to a plurality of data sets stored in a memory and each data set in the plurality may correspond to a type table defining data types in the corresponding data set. The method may further include determining that a first data type of the first data is not in a first type table corresponding to the first data set and generating an identifier corresponding to the first data type. The identifier may identify uses of the first data type within each data set in the plurality and may be a standardized value that is used by each data set in the plurality. The method may also include inserting the identifier into the first type table.

    Inferring graph topologies
    3.
    发明授权
    Inferring graph topologies 审中-公开

    公开(公告)号：US10671668B2

    公开(公告)日：2020-06-02

    申请号：US15206637

    申请日：2016-07-11

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Luis Miguel Vaquero Gonzalez ,  Marco Aurelio Barbosa Fagnani Gomes Lotz ,  Brian Quentin Monahan

    IPC: G06F16/901 ,  G06F16/22 ,  G06F16/248

    Abstract: Example embodiments relates to method and systems to infer graph topologies. A computing device for inferring a graph topology, comprises a physical processor that executes machine readable instructions that cause the computing device to process a set of unclassified tables. For each table the computing device determines a primary key comprising a set of columns of a table being analyzed, determines a set of foreign keys, each foreign key comprising a column of the analyzed table, and identifies a parameter based on the analyzed table, the primary key and the set of foreign keys. The parameter may comprise a node identification, a set of node attributes, a set of edges without attributes, a set of edges with attributes or a set of edge attributes. The computing device can cause the display of the graph topology based on the processed set of unclassified tables.

    Memory integrity monitoring
    6.
    发明授权
    Memory integrity monitoring 有权

    公开(公告)号：US10248814B2

    公开(公告)日：2019-04-02

    申请号：US15415450

    申请日：2017-01-25

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Geoffrey Ndu ,  Adrian Shaw ,  Brian Quentin Monahan

    IPC: H04L9/06 ,  H04L9/32 ,  G06F21/60 ,  G06F21/64

    Abstract: In one example in accordance with the present disclosure, a system comprises a first memory module and a first memory integrity monitoring processor, embedded to the first memory module, to receive a second hash corresponding to a second memory module. The second hash includes a second sequence number for reconstruction of a final hash value and the second hash is not sequentially a first number in a sequence for reconstruction of the final hash value. The first processor may receive a third hash corresponding to a third memory module. The third hash includes a third sequence number for reconstruction of the final hash value and the third hash is received after the second hash. The first processor may determine if the second hash can be combined with the third hash, combine the second hash and third hash into a partial hash reconstruct the final hash value using the partial hash.

    SCHEDULING HETEROGENOUS PROCESSORS
    7.
    发明申请
    SCHEDULING HETEROGENOUS PROCESSORS 审中-公开

    公开(公告)号：US20180225150A1

    公开(公告)日：2018-08-09

    申请号：US15748478

    申请日：2015-07-27

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Patrick Goldsack ,  Brian Quentin Monahan ,  Granville Barnett

    IPC: G06F9/50 ,  G06F9/54 ,  G06F8/41

    CPC classification number: G06F9/5033 ,  G06F8/41 ,  G06F9/46 ,  G06F9/5044 ,  G06F9/544

    Abstract: An example computing device comprises a first processing unit having first capabilities, a second processing unit having second capabilities, and a shared memory accessible by the first processing unit and the second processing unit. The shared memory stores data objects in association with type information indicating the data type of the data objects. The example computing device further comprises an instruction set to, when executed by a processing unit of the computing device, select one of the first processing unit and the second processing unit to perform a computation of a particular type, using data of a particular type stored in the shared memory, wherein the selection is performed based on a predefined affinity of the first processing unit for the particular computation type and/or the particular data type and a predefined affinity of the second processing unit for the particular computation type and/or the particular data type.

    Software validation for untrusted computing systems
    8.
    发明授权
    Software validation for untrusted computing systems 有权

    公开(公告)号：US11496317B2

    公开(公告)日：2022-11-08

    申请号：US15756977

    申请日：2016-01-21

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Chris Tofts ,  Brian Quentin Monahan ,  Adrian John Baldwin

    IPC: G06F21/00 ,  H04L29/06 ,  H04L9/32 ,  G06F21/57 ,  G06F21/53 ,  G06F21/64 ,  G06F21/51

    Abstract: A method of validating software including maintaining, in a trusted computing system, a copy of at least portions of data of the software, the software comprising data in an untrusted computing system. The method includes, with the trusted computing system, specifying selected data from data included in the copy as hash data, generating an executable file for generating a hash based on the specified hash data, executing the executable file to generate a check hash using the specified selected data from the copy as the hash data, and determining whether the software is valid based, at least in part, on a comparison of the check hash to an access hash generated by execution of the executable file by the untrusted computing system using the specified selected data from the untrusted computing system as the hash data.

    Scheduling heterogenous processors
    9.
    发明授权
    Scheduling heterogenous processors 有权

    公开(公告)号：US10558500B2

    公开(公告)日：2020-02-11

    申请号：US15748478

    申请日：2015-07-27

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Patrick Goldsack ,  Brian Quentin Monahan ,  Granville Barnett

    IPC: G06F9/46 ,  G06F9/50 ,  G06F8/41 ,  G06F9/54

    Abstract: An example computing device comprises a first processing unit having first capabilities, a second processing unit having second capabilities, and a shared memory accessible by the first processing unit and the second processing unit. The shared memory stores data objects in association with type information indicating the data type of the data objects. The example computing device further comprises an instruction set to, when executed by a processing unit of the computing device, select one of the first processing unit and the second processing unit to perform a computation of a particular type, using data of a particular type stored in the shared memory, wherein the selection is performed based on a predefined affinity of the first processing unit for the particular computation type and/or the particular data type and a predefined affinity of the second processing unit for the particular computation type and/or the particular data type.

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