Volatile memory cache line directory tags

    公开(公告)号:US10936493B2

    公开(公告)日:2021-03-02

    申请号:US16445830

    申请日:2019-06-19

    Abstract: An example memory system may include a central processing unit (CPU) comprising a CPU cache, a storage class memory, a volatile memory and a memory controller. The memory controller is to store, in the storage class memory, a first cache line including first data and a first directory tag corresponding to the first data. The memory controller is to further store, in the storage class memory, a second cache line including second data and a second directory tag corresponding to the second data. The memory controller is to store, in the volatile memory, a third cache line that comprises the first directory tag and the second directory tag, the third cache line excluding the first data and the second data.

    LOAD DISCOVERY
    3.
    发明申请
    LOAD DISCOVERY 审中-公开

    公开(公告)号:US20170212569A1

    公开(公告)日:2017-07-27

    申请号:US15328375

    申请日:2014-10-31

    Abstract: Example implementations relate to load discovery. For example, a load discovery system can include a shared backup power supply controlled by a backup power control module, and a node coupled to the shared backup power supply, wherein the node supports a plurality of loads, and the shared backup power supply powers the plurality of loads when the node is powered off, and a baseboard management control (BMC) unit coupled to the node, the BMC unit to discover the plurality of loads.

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