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    Backplane interface sets
    1.
    发明授权
    Backplane interface sets 有权

    公开(公告)号：US10901932B2

    公开(公告)日：2021-01-26

    申请号：US15119801

    申请日：2014-04-23

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Brian T Purcell ,  David M Koonce ,  Barry L Olawsky ,  Michael White ,  Quoc Hung C Vu ,  Kyran Wilfred Fey, Jr.

    IPC: G06F13/40 ,  H05K7/14

    Abstract: An example device in accordance with an aspect of the present disclosure includes at least one interface set, including a first interface, at least one second interface, and at least one third interface. A first portion of the first interface is coupled to a second portion of the at least one second interface. A second portion of the first interface is coupled to a first portion of the at least one third interface. The first portion of the first interface is isolated from the second portion of the first interface, the first portion of the second interface is isolated from the second portion of the second interface, and the first portion of the third interface is isolated from the second portion of the third interface.

    Cache management
    2.
    发明授权
    Cache management 有权

    公开(公告)号：US10296240B2

    公开(公告)日：2019-05-21

    申请号：US15117585

    申请日：2014-04-28

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Nathaniel S DeNeui ,  Michael White ,  Jeffrey A Plank

    IPC: G06F12/0888 ,  G06F3/06

    Abstract: A storage controller for cache management that includes a cache memory and a cache management module. The cache management module to, on receipt of region specification requests from hosts, extract from the region specification requests cache rules for management of regions of data storage of a storage array, and on receipt of data operation requests from hosts, process the data operation requests based on the extracted cache rules.

    BACKPLANE INTERFACE SETS
    4.
    发明申请
    BACKPLANE INTERFACE SETS 审中-公开
    背板接口

    公开(公告)号：US20170052919A1

    公开(公告)日：2017-02-23

    申请号：US15119801

    申请日：2014-04-23

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Brian T Purcell ,  David M Koonce ,  Barry L Olawsky ,  Michael White ,  Quoc Hung C Vu ,  Kyran Wilfred Fey, JR.

    IPC: G06F13/40 ,  H05K7/14

    CPC classification number: G06F13/4068 ,  G06F13/4022 ,  H05K7/1438

    Abstract: An example device in accordance with an aspect of the present disclosure includes at least one interface set, including a first interface, at least one second interface, and at least one third interface. A first portion of the first interface is coupled to a second portion of the at least one second interface. A second portion of the first interface is coupled to a first portion of the at least one third interface. The first portion of the first interface is isolated from the second portion of the first interface, the first portion of the second interface is isolated from the second portion of the second interface, and the first portion of the third interface is isolated from the second portion of the third interface.

    Abstract translation: 根据本公开的一个方面的示例性设备包括至少一个接口组，包括第一接口，至少一个第二接口和至少一个第三接口。 第一接口的第一部分耦合到至少一个第二接口的第二部分。 第一接口的第二部分耦合到至少一个第三接口的第一部分。 第一接口的第一部分与第一接口的第二部分隔离，第二接口的第一部分与第二接口的第二部分隔离，并且第三接口的第一部分与第二接口的第二部分隔离 的第三个界面。

    CACHE MANAGEMENT
    5.
    发明申请
    CACHE MANAGEMENT 审中-公开
    缓存管理

    公开(公告)号：US20160357463A1

    公开(公告)日：2016-12-08

    申请号：US15117585

    申请日：2014-04-28

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Nathaniel S DeNeui ,  Michael White ,  Jeffrey A Plank

    IPC: G06F3/06 ,  G06F12/0888

    CPC classification number: G06F3/0619 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0888 ,  G06F2212/6046

    Abstract: A storage controller for cache management that includes a cache memory and a cache management module. The cache management module to, on receipt of region specification requests from hosts, extract from the region specification requests cache rules for management of regions of data storage of a storage array, and on receipt of data operation requests from hosts, process the data operation requests based on the extracted cache rules.

    Abstract translation: 一种用于高速缓存管理的存储控制器，其包括高速缓冲存储器和高速缓存管理模块。 高速缓存管理模块在接收到来自主机的区域规范请求时，从区域规范提取请求缓存规则用于管理存储阵列的数据存储区域，以及在接收到来自主机的数据操作请求时，处理数据操作请求 基于提取的缓存规则。

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