公开(公告)号：US20200084876A1

公开(公告)日：2020-03-12

申请号：US16126424

申请日：2018-09-10

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： David W. Engler ,  Stephen F. Contreras

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/28

Abstract: A printed circuit board having a substrate layer, at least one electrically conductive trace disposed on the substrate layer, and a solder mask layer disposed over the substrate layer and the electrically conductive trace, wherein the solder mask later includes a void region over at least a portion of the electrically conductive trace. Also, a method of optimizing printed circuit board designing including selecting printed circuit board data comprising at least a solder mask layer area, varying the solder mask layer area, determining an insertion loss value for each varied solder mask layer area, comparing the insertion loss values for each varied solder mask layer area, and selecting a solder mask layer area based on the comparing.

公开(公告)号：US10757801B2

公开(公告)日：2020-08-25

申请号：US16126424

申请日：2018-09-10

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： David W. Engler ,  Stephen F. Contreras

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/28

Abstract: A printed circuit board having a substrate layer, at least one electrically conductive trace disposed on the substrate layer, and a solder mask layer disposed over the substrate layer and the electrically conductive trace, wherein the solder mask later includes a void region over at least a portion of the electrically conductive trace. Also, a method of optimizing printed circuit board designing including selecting printed circuit board data comprising at least a solder mask layer area, varying the solder mask layer area, determining an insertion loss value for each varied solder mask layer area, comparing the insertion loss values for each varied solder mask layer area, and selecting a solder mask layer area based on the comparing.

公开(公告)号：US09928897B2

公开(公告)日：2018-03-27

申请号：US15500070

申请日：2015-02-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Reza M. Bacchus ,  Melvin K. Benedict ,  Stephen F. Contreras ,  Eric L. Pope ,  Chi K. Sides ,  Chun-Pin Huang

IPC: G11C5/06 ,  G11C11/4074 ,  G11C5/10

CPC classification number: G11C11/4074 ,  G11C5/04 ,  G11C5/06 ,  G11C5/10 ,  G11C5/14 ,  G11C5/147 ,  G11C11/401

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. At least one stitching capacitor is to couple the first power plane to a second power plane.