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公开(公告)号：US20190102207A1
公开(公告)日：2019-04-04
申请号：US16194169
申请日：2018-11-16
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Jeffrey Kevin Jeansonne , Valiuddin Ali , Lan Wang , Baraneedharan Anbazhagan , Patrick L. Gibbons
CPC classification number: G06F9/44505 , G06F11/1417 , G06F21/44 , G06F21/572 , G06F21/575 , G06F21/6218 , G06F21/79 , G06F2221/2141 , H04L9/0643 , H04L9/3242
Abstract: Examples herein disclose receiving a basic input output system (BIOS) policy change and authorizing the BIOS policy change. Upon the authorization of the BIOS policy change, a first copy of the BIOS policy is stored in a first memory accessible by a central processing unit. Additionally, a second copy of the BIOS policy change is transmitted for storage in a second memory electrically isolated from the central processing unit.
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公开(公告)号：US20240430094A1
公开(公告)日：2024-12-26
申请号：US18684784
申请日：2021-09-22
Applicant: Hewlett-Packard Development Company, L.P.
Abstract: An example storage medium is described, wherein the storage medium comprises instructions that, when executed cause a processor of an electronic device to store a private key in a first memory of the electronic device. The controller also stores an encrypted version of a password and validity information defining a condition to the password's validity in a second memory of the electronic device. During a boot process of the electronic device, the controller may detect a failure to decrypt data stored in a third memory and, upon this detection, decrypt the encrypted version of the password using the private key, and determine, using the validity information, whether the password is valid. If the password is valid, the controller may input the decrypted password to a decryption service, wherein the decryption service is to decrypt the data stored in the third memory.
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公开(公告)号：US20240069891A1
公开(公告)日：2024-02-29
申请号：US18260679
申请日：2021-01-21
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： Wei Ze Liu , Rosilet Retnamoni Braduke , Baraneedharan Anbazhagan , Mason Gunyuzlu
CPC classification number: G06F8/65 , H04L9/3247
Abstract: An example electronic device includes a storage circuit, a central processing unit (CPU) coupled to the storage circuit, and a controller coupled to the storage circuit. The CPU is to receive a Basic Input/Output System (BIOS) update image for the electronic device, verify a signature of the BIOS update image, and responsive to verification of the BIOS update image, store a portion of the BIOS update image in the storage circuit. The controller is to obtain the portion of the BIOS update image from the storage circuit, and program the portion of the BIOS update image to a BIOS component of the electronic device.
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公开(公告)号：US11418335B2
公开(公告)日：2022-08-16
申请号：US17052367
申请日：2019-02-01
Applicant: Hewlett-Packard Development Company, L.P.
Abstract: In some examples, a device includes a memory, a processor, and a controller separate from the processor to derive a security credential based on information comprising a key accessible by the controller. The controller communicates the derived security credential in a secure manner to a program code executable on the processor, and uses the derived security credential to protect data stored in the memory against unauthorized access.
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公开(公告)号：US20210359854A1
公开(公告)日：2021-11-18
申请号：US17052367
申请日：2019-02-01
Applicant: Hewlett-Packard Development Company, L.P.
Abstract: In some examples, a device includes a memory, a processor, and a controller separate from the processor to derive a security credential based on information comprising a key accessible by the controller. The controller communicates the derived security credential in a secure manner to a program code executable on the processor, and uses the derived security credential to protect data stored in the memory against unauthorized access.
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Patent Agency Ranking
公开(公告)号：US20180373900A1
公开(公告)日：2018-12-27
申请号：US15771348
申请日：2016-02-19
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： Dallas M Barlow , Stanley Hyojun Park , Christopher H Stewart , Baraneedharan Anbazhagan , Scott B Marcak , Richard A Bramley, JR.
Abstract: A computer system includes an independent compute core; and an isolated secure data storage device to store data accessible only to the independent compute core. The independent compute core is to open an Application Program Interface (API) during runtime of the computer system in response to receiving a verified message containing secure data to be written to the secure data storage device.
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公开(公告)号：US09983886B2
公开(公告)日：2018-05-29
申请号：US14892223
申请日：2013-07-31
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Baraneedharan Anbazhagan , Christopher H Stewart
CPC classification number: G06F9/4401 , G06F8/654 , G06F12/1458 , G06F21/572 , G06F2212/1052
Abstract: It is determined whether an updated first boot phase code is present. The updated first boot phase code is validated. In response to the validating, a current version of the first boot phase code is updated using the updated first boot phase code.
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公开(公告)号：US20250030674A1
公开(公告)日：2025-01-23
申请号：US18684768
申请日：2021-09-22
Applicant: Hewlett-Packard Development Company, L.P.
Abstract: An example storage medium is described, wherein the storage medium comprises instructions that, when executed cause a processor of an electronic device to store authentication data in a first memory of the electronic device. Upon detecting a failure to decrypt information, the processor is to perform an authentication with a webservice, receive a recovery code, and input the recovery code to a recovery service. The recovery code is obscured from the user.
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公开(公告)号：US11868276B2
公开(公告)日：2024-01-09
申请号：US17830730
申请日：2022-06-02
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Richard A Bramley , Baraneedharan Anbazhagan , Valiuddin Ali
CPC classification number: G06F12/1416 , G06F12/0246 , G06F2212/1052 , G06F2212/7207
Abstract: An example non-transitory computer readable storage medium comprising instructions that when executed cause a processor of a computing device to: in response to a trigger of a system management mode (SMM), verify all processor threads have been pulled into the SMM; in response to a successful verification, enable write access to a non-volatile memory of the computing device via two registers, where the writing access is disabled upon booting of the computing device; and upon exiting the SMM, disable the write access via the two registers.
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公开(公告)号：US11409876B2
公开(公告)日：2022-08-09
申请号：US16603283
申请日：2017-04-24
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： Christopher H Stewart , Baraneedharan Anbazhagan , Lan Wang
Abstract: The update progress of a basic input/output system (BIOS) is displayed on a display screen. A first chipset lock is applied to a first region of a shared serial peripheral interface (SPI) chip of the BIOS of a computer system containing a first program of instructions. A system management memory mode lock is applied to a second and a third region of the shared SPI chip containing a second and third programs of instructions respectively. The second program of instructions is updated, and control of the BIOS is transferred to the updated second program of instructions. The updated second program of instructions updates the first program of instructions. The BIOS update progress visual is displayed on the display screen of the computer system while updating the first program of instructions.
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