公开(公告)号：US20150378913A1

公开(公告)日：2015-12-31

申请号：US14764651

申请日：2013-03-20

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Norman P. Jouppi ,  Sheng Li ,  Ke Chen

IPC: G06F12/08

CPC classification number: G06F12/0844 ,  G06F12/08 ,  G06F12/0811 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/283 ,  G06F2212/304 ,  G06F2212/604

Abstract: A memory system includes a plurality of memory nodes provided at different hierarchical levels of the memory system, each of the memory nodes including a corresponding memory storage and a cache. A memory node at a first of the different hierarchical levels is coupled to a processor with lower communication latency than a memory node at a second of the different hierarchical levels. The memory nodes are to cooperate to decide which of the memory nodes is to cache data of a given one of the memory nodes.

Abstract translation: 存储器系统包括在存储器系统的不同层级提供的多个存储器节点，每个存储器节点包括对应的存储器存储器和高速缓存。 处于不同等级级别的第二级的存储器节点被耦合到具有比存储器节点低的通信延迟的处理器。 存储器节点将协作以确定哪个存储器节点将缓存给定的一个存储器节点的数据。