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公开(公告)号:US11633949B2
公开(公告)日:2023-04-25
申请号:US16973999
申请日:2018-09-24
Applicant: Hewlett-Packard Development Company, L.P.
Inventor: Eric Martin , James R Przybyla , Rogelio Cicili
Abstract: Examples include a fluidic die. The fluidic die comprises an array of field effect transistors. Connecting members electrically connect at least some of the field effect transistors of the array of field effect transistors, and the field effect transistors of the array are arranged into respective sets of field effect transistors. The fluidic die further comprises a first fluid actuator connected to a first set of field effect transistors having a first number of field effect transistors. The die includes a second fluid actuator connected to a second respective set of field effect transistors having a second number of field effect transistors that is different than the first number of field effect transistors.
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公开(公告)号:US20240286402A1
公开(公告)日:2024-08-29
申请号:US18572767
申请日:2021-07-06
Applicant: Hewlett-Packard Development Company, L.P.
Inventor: Eric Thomas Martin , James Michael Gardner , Rogelio Cicili
CPC classification number: B41J2/04548 , G11C5/147
Abstract: An integrated circuit includes a plurality of fluid actuation devices, a plurality of memory cells, a high-voltage high-power supply node, and a high-voltage low-power supply node. The high-voltage high-power supply node is to supply a first voltage and a first maximum current to the plurality of fluid actuation devices. The high-voltage low-power supply node is to supply a second voltage and a second maximum current to the plurality of memory cells.
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公开(公告)号:US20230071745A1
公开(公告)日:2023-03-09
申请号:US17799708
申请日:2020-03-09
Applicant: Hewlett-Packard Development Company, L.P.
Inventor: Eric Thomas Martin , Gary G. Lutnesky , James R. Przybyla , Rogelio Cicili
Abstract: In one example in accordance with the present disclosure, a fluidic die is described. The fluidic die includes a substrate and fluid actuators, the fluid actuators being disposed on the substrate. The fluidic die also includes a bond pad region defined on the substrate. The bond pad region includes a high aspect ratio power delivery bond pad with multiple bonding sites and a high aspect ratio power return bond pad with multiple bonding sites.
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公开(公告)号:US11345157B2
公开(公告)日:2022-05-31
申请号:US16768205
申请日:2019-10-25
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Sirena Lu , Rogelio Cicili , James Michael Gardner , Scott A. Linn
IPC: B41J2/175 , B41J2/045 , G06F13/42 , G06F21/44 , G06F1/12 , G06F1/08 , H03K19/0175 , B33Y30/00 , B29C64/259 , G06F3/12 , G01F23/24 , G01F23/80
Abstract: A logic circuitry package for a replaceable print apparatus component comprises at least one logic circuit and an interface to communicate with a print apparatus logic circuit. The at least one logic circuit is configured to receive, via the interface, calibration parameters including an offset parameter and a sensor ID. The at least one logic circuit is configured to output, via the interface, a digital value corresponding to the sensor ID and offset based on the offset parameter.
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公开(公告)号:US20210276321A1
公开(公告)日:2021-09-09
申请号:US16317891
申请日:2016-10-24
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Daryl E Anderson , Eric Martin , James Michael Gardner , Rogelio Cicili
IPC: B41J2/045
Abstract: Example implementations relate to current leakage testing of a fluid ejection die. For example, a fluid ejection die may include plurality of nozzles, each nozzle among the plurality of nozzles including a nozzle sensor and a fluid ejector. The plurality of nozzle sensors may comprise a first subset and a second subset, each nozzle sensor among the plurality of nozzle sensors of the first subset may be electrically coupled to a first control line by a respective switch among a first group of switches, and each nozzle sensor among the plurality of nozzle sensors of the second subset may be electrically coupled to a second control line by a respective switch among a second group of switches. The fluid ejection die may include a control circuit to perform a current leakage test of the plurality of nozzles using the first control line and the second control line.
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公开(公告)号:US20210206161A1
公开(公告)日:2021-07-08
申请号:US16973999
申请日:2018-09-24
Applicant: Hewlett-Packard Development Company, L.P.
Inventor: Eric Martin , James R Przybyla , Rogelio Cicili
Abstract: Examples include a fluidic die. The fluidic die comprises an array of field effect transistors. Connecting members electrically connect at least some of the field effect transistors of the array of field effect transistors, and the field effect transistors of the array are arranged into respective sets of field effect transistors. The fluidic die further comprises a first fluid actuator connected to a first set of field effect transistors having a first number of field effect transistors. The die includes a second fluid actuator connected to a second respective set of field effect transistors having a second number of field effect transistors that is different than the first number of field effect transistors.
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公开(公告)号:US10946651B2
公开(公告)日:2021-03-16
申请号:US16619341
申请日:2017-07-20
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Eric Martin , James Gardner , Rogelio Cicili
Abstract: A fluidic die includes a sense architecture having a global sense block to provide an analog reference signal and an array of distributed sense blocks. Each distributed sense block is to receive a same set of addresses via an address bus and each is to receive a corresponding sense enable signal having an enable value or a disable value. Each distributed sense block includes an array of sensors, each sensor corresponding to a different address of the set of addresses and a sample circuit to apply the analog reference signal to the sensor corresponding to the address on the address bus when the corresponding sense enable signal has the enable value, and provide to the global sense block an analog sense signal from the sensor resulting from application of the analog reference signal.
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公开(公告)号:US20220118760A1
公开(公告)日:2022-04-21
申请号:US17413687
申请日:2019-06-19
Applicant: Hewlett-Packard Development Company, L.P.
Inventor: Eric Thomas Martin , Rogelio Cicili
IPC: B41J2/045 , H03K3/356 , H03K17/687
Abstract: In example implementations, an apparatus is provided. The apparatus includes a first low voltage control block, a second low voltage control block, a primitive level shifter coupled to the first low voltage control block, a plurality of nozzle level shifters coupled to the primitive level shifter and a second low voltage control block, and a high side switch (HSS) control coupled to each one of the plurality of nozzle level shifters and the second low voltage control block. The plurality of nozzle level shifters are communicatively coupled to each other. The primitive shifter is to enable a selected nozzle level shifter to fire a respective HSS control circuit of the selected nozzle level shifter and to direct a tail current from the selected nozzle level shifter.
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公开(公告)号:US20210362492A1
公开(公告)日:2021-11-25
申请号:US17058692
申请日:2018-11-16
Applicant: Hewlett-Packard Development Company, L.P.
Inventor: James Michael Gardner , Daryl E. Anderson , Eric Thomas Martin , Rogelio Cicili
Abstract: Examples of a fluidic die for temperature sensing are described herein. In some examples, a fluidic die may include a plurality of thermal sense modules. In some examples, each of the thermal sense modules includes a diode connected between a first switch and a second switch. In some examples, the fluidic die includes a differential amplifier to output a temperature voltage signal. In some examples, a first input of the differential amplifier is connected to the first switch of each of the thermal sense modules and a second input of the differential amplifier is connected to the second switch of each of the thermal sense modules.
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公开(公告)号:US20210246013A1
公开(公告)日:2021-08-12
申请号:US17251236
申请日:2018-09-24
Applicant: Hewlett-Packard Development Company, L.P.
Inventor: Eric Martin , Rogelio Cicili , Tsuyoshi Yamashita
Abstract: Examples include a fluidic die. The fluidic die comprises an array of field effect transistors including field effect transistors of a first size and field effect transistors of a second size. At least one connecting member interconnects at least some of the field effect transistors of the array of field effect transistors. The fluidic die further comprises a first fluid actuator connected to a first set of field effect transistors having at least one field effect transistor of the first size. The die includes a second fluid actuator connected to a second respective set of field effect transistors having a first respective field effect transistor of the second size interconnected to at least one other field effect transistor of the array.
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