公开(公告)号：US20170364610A1

公开(公告)日：2017-12-21

申请号：US15622805

申请日：2017-06-14

Applicant: Hitachi, Ltd.

Inventor： Takumi UEZONO ,  Tadanobu TOBA ,  Yusuke KANNO ,  Masahiro SHIRAISHI ,  Hideo HARADA ,  Satoshi NISHIKAWA ,  Toru MOTOYA

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5022 ,  G06F17/5045 ,  G06F17/5054 ,  G06F17/5081 ,  G06F2217/02 ,  G06F2217/66

Abstract: Provided is a technology capable of reducing the number of resources necessary for logic implementation in a control device. A semiconductor LSI design device generates a combinational circuit configured with functional blocks defined by a functional block library from an application specification, allocates an operation order of each functional block in the combinational circuit under a condition for starting an operation of a functional block connected to an input pin after ending the operation, converts into a sequence circuit which uses the functional block twice or more in a time division manner, extracts the operation order at a time of execution of the sequential circuit, and determines whether the operation order allocated to the combinational circuit coincide with the extracted operation execution order.

公开(公告)号：US20230082529A1

公开(公告)日：2023-03-16

申请号：US17795025

申请日：2020-08-18

Applicant: Hitachi, Ltd.

Inventor： Takumi UEZONO ,  Masahiro SHIRAISHI ,  Tadanobu TOBA ,  Satoshi NISHIKAWA ,  Keisuke YAMAMOTO

IPC: G06F11/10 ,  G06F11/07

Abstract: The operational continuity of a programmable device, and a controller using the same is enhanced. A programmable device is configured with: an error check mechanism that detects, and notifies an error from redundantized user logic blocks; a previous value retaining section that is connected to an output terminal of a last user logic block, and takes in, and outputs an output value of the user logic blocks in each control period; a CRAM check section that receives a scan interrupt due to an error occurrence notification received from the error check mechanism, reads a scan region on the CRAM, implements error detection, and error correction, and notifies a success or failure of the error correction; and an error handling section that transmits an instruction for retaining a previous output of the user logic blocks to the previous value retaining section when the error occurrence notification is received, transmits an instruction for cancelling previous-value retention to the previous value retaining section, and also transmits a logical reset instruction to a user logic block relevant to an error when a notification of a success of the error correction is received from the CRAM check section.

公开(公告)号：US20170357567A1

公开(公告)日：2017-12-14

申请号：US15621519

申请日：2017-06-13

Applicant: HITACHI, LTD.

Inventor： Toru MOTOYA ,  Masahiro SHIRAISHI ,  Satoshi NISHIKAWA ,  Keisuke YAMAMOTO ,  Tadanobu TOBA ,  Takumi UEZONO ,  Hideo HARADA ,  Yusuke KANNO

IPC: G06F11/36 ,  G06F17/50 ,  G06F9/30

CPC classification number: G06F11/3652 ,  G06F9/3017 ,  G06F11/3636 ,  G06F17/504 ,  G21C17/00 ,  G21D3/001 ,  Y02E30/40

Abstract: A verification method for an application logic provided with one or more macro logics configured to perform a predetermined operation, a macro operation control unit configured to instruct the one or more macro logics to start the operation to cause the one or more macro logics to perform the operation, and an operation data storage area configured to store data. In the application logic, static verification by property description of a formal verification language is performed for each of the one or more macro logic, the macro operation control unit, and the operation data storage area, and dynamic verification by simulation is further performed for at least one of the one or more macro logics.

公开(公告)号：US20190332727A1

公开(公告)日：2019-10-31

申请号：US16389332

申请日：2019-04-19

Applicant: HITACHI, LTD.

Inventor： Takumi UEZONO ,  Tadanobu TOBA ,  Masahiro SHIRAISHI ,  Hideo HARADA ,  Satoshi NISHIKAWA

IPC: G06F17/50 ,  H01L27/02

Abstract: Provided is a semiconductor LSI design device that includes: a unit that generates a combinational circuit constituted by combining function blocks defined by a function block library from an application specification, by assigning connection information on an operation order of the function blocks; a unit that converts the combinational circuit to operation order information that is applicable to a sequential circuit in which a function block is used a plurality of times in a time-division manner; a unit that inversely converts the generated operation order information to a combinational circuit; a unit that verifies logical equivalence of the combinational circuit and the inversely converted combinational circuit; and a unit that combines the operation order information, the sequential circuit and a function block.

公开(公告)号：US20180115405A1

公开(公告)日：2018-04-26

申请号：US15728592

申请日：2017-10-10

Applicant: Hitachi, Ltd.

Inventor： Katsunobu NATORI ,  Tetsuya NAKAJIMA ,  Satoshi NISHIKAWA ,  Masahiro SHIRAISHI ,  Hideo HARADA

IPC: H04L5/14 ,  H04L1/00 ,  G06F7/57

CPC classification number: H04L5/14 ,  G06F7/57 ,  G06F11/0796 ,  G06F11/1633 ,  H04L1/0061

Abstract: A control system includes an arithmetic device configured of an A system arithmetic unit including a data dividing unit, a B system arithmetic unit including a data dividing unit, and an A system communication control unit including a data combining unit and a collation unit, wherein the A system arithmetic unit and the B system arithmetic unit have a duplex configuration, the A system arithmetic unit and the B system arithmetic unit are separated by a gap, a frame output from the A system arithmetic unit is transmitted to a B system communication control unit through the A system communication control unit and an interface element, and a frame output from the B system arithmetic unit is transmitted to the A system communication control unit through the B system communication control unit and an interface element.