公开(公告)号：US20240193454A1

公开(公告)日：2024-06-13

申请号：US18286836

申请日：2022-02-01

Applicant: Hitachi, Ltd.

Inventor： Yusuke KANNO ,  Hiroyuki MIZUNO ,  Chihiro YOSHIMURA

IPC: G06N10/40 ,  G06N10/20

CPC classification number: G06N10/40 ,  G06N10/20

Abstract: A quantum computer system includes: a virtual quantum computer that simulates an operation of an actual quantum computer that executes a quantum operation using a quantum bit group based on a predetermined parameter; and a control device that controls the actual quantum computer and the virtual quantum computer, wherein the virtual quantum computer includes an estimation unit that estimates a state of a target quantum bit in the quantum bit group by simulating the operation of the actual quantum computer, and the control device includes a feedback control unit that changes the parameter and transmits the changed parameter to the virtual quantum computer until a deviation between an estimation state of the target quantum bit by the estimation unit and a quantum operation result from the actual quantum computer becomes a first design value or less.

公开(公告)号：US20230297873A1

公开(公告)日：2023-09-21

申请号：US18073641

申请日：2022-12-02

Applicant: Hitachi, Ltd.

Inventor： Gou SHINKAI ,  Ryuta TSUCHIYA ,  Yusuke KANNO

IPC: G06N10/60

CPC classification number: G06N10/60

Abstract: Provided is a control method of a quantum bit including, when a two-quantum bit computation is performed on a plurality of pairs of quantum bits by a plurality of barrier transistors controlled collectively, selectively performing a one-quantum bit computation on a quantum bit selected from the plurality of pairs of quantum bits to selectively perform a two-quantum bit computation on a desired quantum bit pair selected from the plurality of pairs of quantum bits.

公开(公告)号：US20170364610A1

公开(公告)日：2017-12-21

申请号：US15622805

申请日：2017-06-14

Applicant: Hitachi, Ltd.

Inventor： Takumi UEZONO ,  Tadanobu TOBA ,  Yusuke KANNO ,  Masahiro SHIRAISHI ,  Hideo HARADA ,  Satoshi NISHIKAWA ,  Toru MOTOYA

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5022 ,  G06F17/5045 ,  G06F17/5054 ,  G06F17/5081 ,  G06F2217/02 ,  G06F2217/66

Abstract: Provided is a technology capable of reducing the number of resources necessary for logic implementation in a control device. A semiconductor LSI design device generates a combinational circuit configured with functional blocks defined by a functional block library from an application specification, allocates an operation order of each functional block in the combinational circuit under a condition for starting an operation of a functional block connected to an input pin after ending the operation, converts into a sequence circuit which uses the functional block twice or more in a time division manner, extracts the operation order at a time of execution of the sequential circuit, and determines whether the operation order allocated to the combinational circuit coincide with the extracted operation execution order.

公开(公告)号：US20160254803A1

公开(公告)日：2016-09-01

申请号：US15028568

申请日：2013-10-16

Applicant: HITACHI, LTD.

Inventor： Yusuke KANNO ,  Takeshi SAKATA ,  Nobuyasu KANEKAWA

IPC: H03K3/037 ,  H03K3/3562

CPC classification number: H03K3/0375 ,  H03K3/0372 ,  H03K3/35625 ,  H03K19/0948 ,  H03K19/17724 ,  H03K19/17728 ,  H03K19/20 ,  H03K19/23

Abstract: Provided is a semiconductor device capable of reducing a penalty associated with ensuring reliability. The semiconductor device includes a latch circuit which has input/output paths of three systems or more independent from each other. The latch circuit includes a plurality of storage elements STE1 to STE3 which are provided on the input/output paths of the three systems or more, respectively, and hold input data in synchronization with a clock signal. At least one storage element (for example, STE1) of the plurality of storage elements STE1 to STE3 includes a majority decision unit (for example, 81a) executing a majority decision using data from the storage elements provided on other input/output paths different from the input/output path thereof and outputs data in which a result of the majority decision is reflected.

Abstract translation: 提供了能够减少与确保可靠性相关联的惩罚的半导体器件。 半导体器件包括具有彼此独立的三个系统或更多个输入/输出路径的锁存电路。 锁存电路包括分别设置在三个或更多个系统的输入/输出路径上的多个存储元件STE1至STE3，并且与时钟信号同步地保持输入数据。 多个存储元件STE1至STE3中的至少一个存储元件（例如，STE1）包括使用来自不同于其它输入/输出路径的其他输入/输出路径上提供的存储元件的数据执行多数决定的多数决定单元（例如，81a） 其输入/输出路径并输出反映多数决定结果的数据。

公开(公告)号：US20180260687A1

公开(公告)日：2018-09-13

申请号：US15761217

申请日：2016-04-26

Applicant: Hitachi, Ltd.

Inventor： Yusuke KANNO ,  Takeshi SAKATA ,  Shigeru NAKAHARA

IPC: G06N3/04 ,  G06N3/08

CPC classification number: G06N3/0454 ,  G06N3/063 ,  G06N3/08

Abstract: Efficient learning of a neural network can be performed. A plurality of DNNs are hierarchically configured, and data of a hidden layer of a DNN of a first hierarchy machine learning/recognizing device is used as input data of a DNN of a second hierarchy machine learning/recognizing device.

公开(公告)号：US20170357567A1

公开(公告)日：2017-12-14

申请号：US15621519

申请日：2017-06-13

Applicant: HITACHI, LTD.

Inventor： Toru MOTOYA ,  Masahiro SHIRAISHI ,  Satoshi NISHIKAWA ,  Keisuke YAMAMOTO ,  Tadanobu TOBA ,  Takumi UEZONO ,  Hideo HARADA ,  Yusuke KANNO

IPC: G06F11/36 ,  G06F17/50 ,  G06F9/30

CPC classification number: G06F11/3652 ,  G06F9/3017 ,  G06F11/3636 ,  G06F17/504 ,  G21C17/00 ,  G21D3/001 ,  Y02E30/40

Abstract: A verification method for an application logic provided with one or more macro logics configured to perform a predetermined operation, a macro operation control unit configured to instruct the one or more macro logics to start the operation to cause the one or more macro logics to perform the operation, and an operation data storage area configured to store data. In the application logic, static verification by property description of a formal verification language is performed for each of the one or more macro logic, the macro operation control unit, and the operation data storage area, and dynamic verification by simulation is further performed for at least one of the one or more macro logics.

公开(公告)号：US20170249760A1

公开(公告)日：2017-08-31

申请号：US15370630

申请日：2016-12-06

Applicant: HITACHI, LTD.

Inventor： Tadanobu TOBA ,  Takumi UEZONO ,  Yusuke KANNO ,  Masahiro SHIRAISHI ,  Hideo HARADA ,  Satoru AKASAKA

IPC: G06T11/20

CPC classification number: G06T11/20 ,  G05B19/0425 ,  G05B2219/24182 ,  G05B2219/24187 ,  G06F3/14 ,  G09G2330/08 ,  G09G2330/12 ,  G09G2340/12

Abstract: The present invention includes a drawing data generating unit, a variation pattern that varies at regular intervals to be displayed, a display unit that displays drawing data, and a comparator that compares whether input signals are coincident, and the drawing data generating unit includes a receiver that receives data from a higher-level device, a drawing control unit that converts the data received from the higher-level device to drawing data, and a drawing memory that stores the drawing data. The drawing data generating unit and the variation pattern are redundantly configured, and the variation pattern is input to the drawing data generating unit. One output signal of the drawing data generating unit regarding drawing data including the variation pattern is transmitted to the display unit, a plurality of output signals from the drawing data generating unit are input to the comparator, and the comparator outputs a comparison result as a detection signal outside. This improves safety and reliability when severe safety criteria are required such as in a case of monitor-display in industrial plant equipment.

公开(公告)号：US20160335145A1

公开(公告)日：2016-11-17

申请号：US15110278

申请日：2014-01-24

Applicant: Hitachi, Ltd.

Inventor： Tadanobu TOBA ,  Kenichi SHIMBO ,  Yusuke KANNO ,  Nobuyasu KANEKAWA ,  Kotara SHIMAMURA ,  Hiromichi YAMADA

IPC: G06F11/07 ,  H03K19/177

CPC classification number: G06F11/079 ,  G06F11/0727 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0754 ,  G06F11/0772 ,  G06F11/0793 ,  H03K19/1776 ,  H03K19/17764

Abstract: The present invention aims to provide a programmable device with a configuration memory that can hold the state of the occurrence abnormal situation that is difficult to assume such as a failure occurring in the programmable device due to the terrestrial radiation of the configuration memory, even during power off, in order to improve the reproducibility in device testing based on the held error information. The programmable device with the configuration memory includes: an error detection section for detecting an error in the configuration memory, and outputting the detected error as well as an address in which the error occurred, as error information; and an error information holding section provided with a non-volatile memory to store the output error information.

Abstract translation: 本发明的目的在于提供一种具有配置存储器的可编程设备，即使在电源期间，由于配置存储器的地面辐射，可以保持难以产生的发生异常情况的状态，例如在可编程设备中发生的故障 以提高基于所保持的错误信息的设备测试中的再现性。 具有配置存储器的可编程设备包括：错误检测部分，用于检测配置存储器中的错误，并将检测到的错误以及发生错误的地址输出作为错误信息; 以及设置有用于存储输出错误信息的非易失性存储器的错误信息保持部。

公开(公告)号：US20160241247A1

公开(公告)日：2016-08-18

申请号：US15025821

申请日：2013-09-30

Applicant: HITACHI, LTD.

Inventor： Yusuke KANNO ,  Nobuyasu KANEKAWA ,  Kotaro SHIMAMURA ,  Tadanobu TOBA ,  Teppei HIROTSU ,  Tsutomu YAMADA

IPC: H03K19/177 ,  H03K19/21

CPC classification number: H03K19/17764 ,  H03K19/17728 ,  H03K19/1776 ,  H03K19/21

Abstract: An object of the present invention is to provide a high reliable/high safe programmable logic device with high error resistance. The present invention provides a programmable logic device that has a plurality of configuration memories. The configuration memories are divided into a plurality of areas and are arranged and a part of the plurality of areas is set to a high reliable area where reliability for a failure of the configuration memory is higher than reliability in the other area.

Abstract translation: 本发明的目的是提供一种具有高抗错误性的高可靠/高安全性的可编程逻辑器件。 本发明提供一种具有多个配置存储器的可编程逻辑器件。 配置存储器被分成多个区域并且被布置，并且多个区域的一部分被设置为高可靠性区域，其中配置存储器的故障的可靠性高于其他区域中的可靠性。