公开(公告)号：US20150349115A1

公开(公告)日：2015-12-03

申请号：US14760166

申请日：2013-01-23

Applicant: HITACHI, LTD.

Inventor： Naoki TEGA ,  Digh HISAMOTO ,  Satoru AKIYAMA ,  Takashi TAKAHAMA ,  Tadao MORIMOTO ,  Ryuta TSUCHIYA

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L29/16 ,  H01L21/265

CPC classification number: H01L29/7813 ,  H01L21/02529 ,  H01L21/047 ,  H01L21/26513 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7811

Abstract: Disclosed herein is a technique for realizing a high-performance and high-reliability silicon carbide semiconductor device. A trenched MISFET with a trench formed into the drift through a p-type body layer 105 includes an n-type resistance relaxation layer 109 covering the bottom portion of the trench, and a p-type field relaxation layer 108. The p-type field relaxation layer 108 is separated from the trench bottom portion via the resistance relaxation layer 109, and is wider than the resistance relaxation layer 109. This achieves a low ON resistance, high reliability, and high voltage resistance at the same time. By forming the field relaxation layer beneath the trench, feedback capacitance can be controlled to achieve a high switching rate and high reliability.

Abstract translation: 这里公开了一种实现高性能和高可靠性的碳化硅半导体器件的技术。 具有通过p型体层105形成在漂移中的沟槽的沟槽MISFET包括覆盖沟槽底部的n型电阻缓和层109和p型场弛豫层108. p型场 松弛层108经由电阻缓和层109与沟槽底部分离，并且比电阻缓和层109宽。这样实现了低导通电阻，高可靠性和高耐压性。 通过在沟槽下方形成场弛豫层，可以控制反馈电容以实现高开关率和高可靠性。