公开(公告)号：US20180331174A1

公开(公告)日：2018-11-15

申请号：US15533964

申请日：2015-02-12

Applicant: HITACHI, LTD.

Inventor： Naoki TEGA ,  Naoki WATANABE ,  Shintaroh SATO

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/04 ,  H02P27/08 ,  H02M7/5387 ,  B60L11/18

CPC classification number: H01L29/063 ,  B60L11/1812 ,  B60L2200/26 ,  B61C3/00 ,  H01L21/0465 ,  H01L21/049 ,  H01L29/06 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/12 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7811 ,  H01L29/7813 ,  H02M7/53871 ,  H02P27/08

Abstract: An object of the present invention is to provide high-performance highly-reliable power semiconductor device.The semiconductor device according to the present invention is provided with a first conductive type semiconductor substrate, a drain electrode formed on a back side of the semiconductor substrate, a drift layer of the first conductive type formed on a surface side of the semiconductor substrate, a source area of the first conductive type, a current diffused layer of the first conductive type, a body layer of a second conductive type reverse to the first conductive type in contact with the source area and the current diffused layer, a trench which pierces the source area, the body layer and the current diffused layer, which is shallower than the body layer, and the bottom of which is in contact with the body layer, a high-concentration JFET layer of the first conductive type formed up to a deeper position than a boundary between the current diffused layer and the body layer, electrically connecting the drift layer and the current diffused layer, and having higher impurity concentration than the drift layer, a gate insulating film formed on an inner wall of the trench, and a gate electrode formed on the gate insulating film.

公开(公告)号：US20180090574A1

公开(公告)日：2018-03-29

申请号：US15560428

申请日：2015-05-18

Applicant: HITACHI, LTD.

Inventor： Mieko MATSUMURA ,  Junichi SAKANO ,  Naoki TEGA ,  Yuki MORI ,  Haruka SHIMIZU ,  Keisuke KOBAYASHI

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/36 ,  H01L29/78 ,  H01L29/739

CPC classification number: H01L29/1608 ,  H01L29/0615 ,  H01L29/0684 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/7395 ,  H01L29/7802

Abstract: To solve a problem of realizing a large current and highly reliable power semiconductor device while shrinking a unit cell. A semiconductor device according to the present invention includes a plurality of p-type body regions extending in a first direction. The semiconductor device further includes: a JFET region formed to extend in the first direction between p-type body regions which are adjacent to each other in a second direction orthogonal to the first direction; an n+-type source region formed to extend in the first direction within a p-type body region and separate from an end side surface of the p-type body; and a channel region formed to extend in the first direction and in a top layer portion of a p-type body region between an end side surface of the p-type body region and an end side surface of an n+-type source region.

公开(公告)号：US20170330961A1

公开(公告)日：2017-11-16

申请号：US15524153

申请日：2015-01-19

Applicant: HITACHI, LTD.

Inventor： Naoki TEGA ,  Naoki WATANABE ,  Shintaroh SATO

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8258

CPC classification number: H01L29/66893 ,  H01L21/8258 ,  H01L29/12 ,  H01L29/1608 ,  H01L29/66045 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7825

Abstract: An object of the present invention is to provide high-performance highly-reliable power semiconductor device.The semiconductor device according to the present invention is provided with a semiconductor substrate of a first conductive type, a drain electrode formed on a back side of the semiconductor substrate, a drift layer of the first conductive type formed on a semiconductor substrate, a source area of the first conductive type, a current-diffused layer of the first conductive type electrically connected to the drift layer, a body layer of a second conductive type reverse to the first conductive type in contact with the source area and the current-diffused layer, a trench which pierces the source area, the body layer and the current-diffused layer, which is shallower than the body layer, and the bottom of which is in contact with the body layer, a gate insulating film formed on an inner wall of the trench, a gate electrode formed on the gate insulating film, and a gate insulating film protective layer formed between the current-diffused layer and the gate electrode.

公开(公告)号：US20150318389A1

公开(公告)日：2015-11-05

申请号：US14651555

申请日：2012-12-28

Applicant: HITACHI, LTD.

Inventor： Ryuta TSUCHIYA ,  Hiroyuki MATSUSHIMA ,  Naoki TEGA ,  Digh HISAMOTO

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7802 ,  H01L21/02529 ,  H01L21/0485 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7813

Abstract: When a gate length is reduced for the purpose of reducing on-resistance in a SiC DOMSFET, it is difficult to achieve both of the reduction of on-resistance by the reduction of gate length and the high element withstand voltage at the same time. In the present invention, a body layer is formed after the source diffusion layer region is formed and then a portion of the source diffusion layer region is recessed. Because of the presence of the body layer, the distances between the source diffusion region and respective end portions can be increased, a depletion layer is effectively expanded, and electric field concentration at the end portions can be suppressed, thereby improving withstand voltage characteristics. Consequently, the present invention can provide a silicon carbide semiconductor device that achieves both of the reduction of channel resistance by the reduction of gate length and the high element withstand voltage at the same time.

Abstract translation: 为了降低SiC DOMSFET中的导通电阻而减小栅极长度，难以同时通过栅极长度的降低和高的元件耐受电压来实现导通电阻的降低。 在本发明中，在形成源极扩散层区域之后形成体层，然后使源极扩散层区域的一部分凹陷。 由于体层的存在，可以增大源极扩散区域和各个端部之间的距离，有效地扩大耗尽层，并且可以抑制端部的电场浓度，从而提高耐电压特性。 因此，本发明可以提供通过同时降低栅极长度和高元件耐受电压来实现沟道电阻降低的碳化硅半导体器件。

公开(公告)号：US20160141371A1

公开(公告)日：2016-05-19

申请号：US14897247

申请日：2013-06-06

Applicant: HITACHI, LTD.

Inventor： Naoki TEGA ,  Keisuke KOBAYASHI ,  Koji FUJISAKI ,  Takashi TAKAHAMA

IPC: H01L29/16 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L21/04 ,  H01L21/02 ,  H01L29/78 ,  H01L29/167 ,  H01L29/10

CPC classification number: H01L29/1608 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/0465 ,  H01L21/0485 ,  H01L29/0619 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7811

Abstract: In order to provide a high-performance and reliable silicon carbide semiconductor device, in a silicon carbide semiconductor device including an n-type SiC epitaxial substrate, a p-type body layer, a p-type body layer potential fixing region and a nitrogen-introduced n-type first source region formed in the p-type body layer, an n-type second source region to which phosphorus which has a solid-solubility limit higher than that of nitrogen and is easily diffused is introduced is formed inside the nitrogen-introduced n-type first source region so as to be separated from both of the p-type body layer and the p-type body layer potential fixing region.

Abstract translation: 为了提供高性能和可靠的碳化硅半导体器件，在包括n型SiC外延衬底，p型体层，p型体层电位固定区和氮化硅电极固定区的碳化硅半导体器件中， 引入形成在p型体层中的n型第一源极区域，在氮 - 氮化物区域内形成n型第二源区，其中具有高于氮的固溶度极限的磷并容易扩散的磷， 引入n型第一源极区域以与p型体层电位固定区域和p型体层电位固定区域分离。

公开(公告)号：US20160111499A1

公开(公告)日：2016-04-21

申请号：US14778058

申请日：2013-03-29

Applicant: HITACHI, LTD.

Inventor： Digh HISAMOTO ,  Keisuke KOBAYASHI ,  Naoki TEGA ,  Toshiyuki OHNO ,  Hirotaka HAMAMURA ,  Mieko MATSUMURA

IPC: H01L29/16 ,  H01L29/78 ,  H01L21/04 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02

CPC classification number: H01L29/1608 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/045 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/0619 ,  H01L29/1033 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/872

Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.

Abstract translation: 使用SiC衬底的MOSFET具有通过由于热氧化施加机械应力而在表面上形成碳过量层的问题，并且碳过量层降低沟道载流子的迁移率。 在本发明中，（1）除去含有碳 - 碳键的层; （2）通过沉积方法形成栅极绝缘膜; 和（3）晶体表面和绝缘膜之间的界面在短时间内在低温下进行界面处理。 由此，有效地消除了引起特性劣化的碳过量层，同时通过使氧化膜和氧氮化物膜进行界面处理，可以有效地消除悬挂键。

公开(公告)号：US20150349115A1

公开(公告)日：2015-12-03

申请号：US14760166

申请日：2013-01-23

Applicant: HITACHI, LTD.

Inventor： Naoki TEGA ,  Digh HISAMOTO ,  Satoru AKIYAMA ,  Takashi TAKAHAMA ,  Tadao MORIMOTO ,  Ryuta TSUCHIYA

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L29/16 ,  H01L21/265

CPC classification number: H01L29/7813 ,  H01L21/02529 ,  H01L21/047 ,  H01L21/26513 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7811

Abstract: Disclosed herein is a technique for realizing a high-performance and high-reliability silicon carbide semiconductor device. A trenched MISFET with a trench formed into the drift through a p-type body layer 105 includes an n-type resistance relaxation layer 109 covering the bottom portion of the trench, and a p-type field relaxation layer 108. The p-type field relaxation layer 108 is separated from the trench bottom portion via the resistance relaxation layer 109, and is wider than the resistance relaxation layer 109. This achieves a low ON resistance, high reliability, and high voltage resistance at the same time. By forming the field relaxation layer beneath the trench, feedback capacitance can be controlled to achieve a high switching rate and high reliability.

Abstract translation: 这里公开了一种实现高性能和高可靠性的碳化硅半导体器件的技术。 具有通过p型体层105形成在漂移中的沟槽的沟槽MISFET包括覆盖沟槽底部的n型电阻缓和层109和p型场弛豫层108. p型场 松弛层108经由电阻缓和层109与沟槽底部分离，并且比电阻缓和层109宽。这样实现了低导通电阻，高可靠性和高耐压性。 通过在沟槽下方形成场弛豫层，可以控制反馈电容以实现高开关率和高可靠性。

公开(公告)号：US20210143255A1

公开(公告)日：2021-05-13

申请号：US17080946

申请日：2020-10-27

Applicant: HITACHI, LTD.

Inventor： Takeru SUTO ,  Naoki TEGA ,  Naoki WATANABE ,  Hiroshi MIKI

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06

Abstract: Provided is a semiconductor device whose performance is improved. A p type body region is formed in an n type semiconductor layer containing silicon carbide, and a gate electrode is formed on the body region with a gate insulating film interposed therebetween. An n type source region is formed in the body region on a side surface side of the gate electrode, and the body region and a source region are electrically connected to a source electrode. A p type field relaxation layer FRL is formed in the semiconductor layer on the side surface side of the gate electrode, and the source electrode is electrically connected to the field relaxation layer FRL. The field relaxation layer FRL constitutes a part of the JFET 2Q which is a rectifying element, and a depth of the field relaxation layer FRL is shallower than a depth of the body region.

公开(公告)号：US20190229211A1

公开(公告)日：2019-07-25

申请号：US16216333

申请日：2018-12-11

Applicant: HITACHI, LTD.

Inventor： Yuan BU ,  Hiroshi MIKI ,  Naoki TEGA ,  Naoki WATANABE ,  Digh HISAMOTO ,  Takeru SUTO

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/417 ,  H01L29/36 ,  H01L29/423 ,  H01L29/47 ,  H01L29/04 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L29/08 ,  H01L29/10

Abstract: A silicon carbide semiconductor device includes an n-type silicon carbide semiconductor substrate, a drain electrode electrically connected to a rear face, an n-type semiconductor layer having a second impurity concentration lower than the first impurity concentration, a p-type first semiconductor region, an n-type second semiconductor region, an n-type third semiconductor region, a trench having a first side face and a second side face opposing to each other and a third side face intersecting with the first side face and the second side face, a gate electrode formed in the trench with a gate insulating film interposed therebetween, a metal layer electrically connected to the third semiconductor region, and a source electrode electrically connecting the second semiconductor region and the metal layer to each other.

公开(公告)号：US20130146897A1

公开(公告)日：2013-06-13

申请号：US13684314

申请日：2012-11-23

Applicant: Hitachi, Ltd.

Inventor： Hiroyuki YOSHIMOTO ,  Ryuta TSUCHIYA ,  Naoki TEGA ,  Digh HISAMOTO ,  Yasuhiro SHIMAMOTO ,  Yuki MORI

IPC: H01L29/16

CPC classification number: H01L29/1608 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/045 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7827

Abstract: A trench groove is formed and a silicon oxide film is buried in the periphery of a channel region of (0001) surface 4h-SiC semiconductor element. The oxide film in the trench groove is defined in such a planar layout that a tensile strain is applied along the direction of the c-axis and a compressive strain is applied along two or more of axes on a plane perpendicular to the c-axis. For example, trench grooves buried with an oxide film may be configured to such a layout that they are in a trigonal shape surrounding the channel, or are arranged symmetrically with respect to the channel as a center when arranged discretely.

Abstract translation: 形成沟槽，在（0001）面4h-SiC半导体元件的沟道区的周围埋置氧化硅膜。 沟槽中的氧化膜以这样的平面布局限定，使得沿着c轴的方向施加拉伸应变，并且沿着与c轴垂直的平面上的两个或更多个轴施加压缩应变。 例如，埋置有氧化物膜的沟槽沟可以被配置为使得它们处于围绕通道的三角形状，或者当离散布置时相对于通道对称地布置为中心。