公开(公告)号：US10094846B2

公开(公告)日：2018-10-09

申请号：US14956663

申请日：2015-12-02

Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION

Inventor： Hitoshi Tokieda ,  Yoshimitsu Takagi ,  Takeshi Shibuya ,  Masashi Akutsu

IPC: G01N35/04 ,  G01N35/10 ,  G01N35/02 ,  G01N35/00

Abstract: A sample-processing system that improves total system processing efficiency, and reduces a sample-processing time, by establishing a functionally independent relationship between a rack conveyance block with rack supply, conveyance, and recovery functions, and a processing block with sample preprocessing, analysis, and other functions. A buffer unit with random accessibility to multiple racks standing by for processing is combined with each of multiple processing units to form a pair, and the system is constructed to load and unload racks into and from the buffer unit through the rack conveyance block so that one unprocessed rack is loaded into the buffer unit and then upon completion of process steps up to automatic retesting, unloaded from the buffer unit. Functional dependence between any processing unit and a conveyance unit is thus eliminated.