公开(公告)号：US09484918B1

公开(公告)日：2016-11-01

申请号：US14834837

申请日：2015-08-25

Applicant: HRL LABORATORIES, LLC

Inventor： Yen-Cheng Kuan ,  Ining Ku ,  Zhiwei A. Xu ,  Susan L. Morton ,  Donald A. Hitko ,  Peter Petre ,  Jose Cruz-Albrecht ,  Alan E. Reamon

IPC: H03K19/003 ,  H03K19/00

CPC classification number: H03K19/00369 ,  H01Q3/26 ,  H01Q3/2682 ,  H03K3/86 ,  H03K19/0016 ,  H04B7/0617 ,  H04B7/0671

Abstract: A pulse domain 1 to 2N demultiplexer has a (i) pair of N stage counters each of which is responsive to an incoming pulse train in the pulse domain, one of the counters being responsive to leading edges of the pulses in the incoming pulse train and the other one of the counters being responsive to trailing edges of the pulses in the incoming pulse train and (ii) a control logic responsive to the states through which the pair of counters count, the control logic including 2N gate arrangements, each of the 2N gate arrangements generating a output signal of the pulse domain 1 to 2N demultiplexer.

Abstract translation: 脉冲域1至2N解复用器具有（i）一对N级计数器，每个N级计数器响应于脉冲域中的输入脉冲序列，其中一个计数器响应于输入脉冲串中的脉冲的前沿， 另一个计数器响应输入脉冲串中的脉冲的后沿，以及（ii）响应于该对计数器计数的状态的控制逻辑，包括2N个门装置的控制逻辑，2N个 门结构产生脉冲域1至2N解复用器的输出信号。