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1.发明授权Method and apparatus for detecting amplitudes and/or phases of recognizable signals in a frequency band or spectrum of interest 有权用于检测感兴趣的频带或频谱中的可识别信号的幅度和/或相位的方法和装置公开(公告)号：US08958764B1
公开(公告)日：2015-02-17
申请号：US13663308
申请日：2012-10-29
Applicant: HRL Laboratories, LLC
Inventor： Zhiwei Xu , Donald A. Hitko , Peter Petre
CPC classification number: H04L27/22
Abstract: A method of and apparatus for detecting signal features including amplitude, phase and timing of recognizable input signals in a frequency band or spectrum of interest. One or more super-regenerative oscillators are provided, each having a center frequency and each detecting signal features of recognizable input signals in the frequency band or spectrum of interest during multiple, successive time slots. The center frequency of each of the one or more super-regenerative oscillators is varied between time slots in a selected sequence, preferably according to a Segmentlet algorithm. The one or more super-regenerative oscillators extract the signal features of each the recognizable input signals in different time slots and/or in different super-regenerative oscillator and with a different time-slot associated center frequency associated with the one or more super-regenerative oscillators, thereby providing a time-frequency-amplitude map of the frequency band or spectrum of interest.
Abstract translation: 一种用于检测包括感兴趣的频带或频谱中的可识别输入信号的幅度，相位和定时的信号特征的方法和装置。 提供一个或多个超再生振荡器，每个超级再生振荡器在多个连续时隙中具有中心频率和每个检测信号特征在感兴趣的频带或频谱中的可识别输入信号。 一个或多个超再生振荡器中的每一个的中心频率在所选序列中的时隙之间是优选的，根据Segmentlet算法。 一个或多个超再生振荡器在不同的时隙和/或不同的超再生振荡器中提取每个可识别的输入信号的信号特征，以及与一个或多个超再生振荡器相关联的不同的时隙相关联的中心频率 振荡器，从而提供感兴趣的频带或频谱的时间 - 频率幅度图。
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公开(公告)号：US10515872B1
公开(公告)日：2019-12-24
申请号：US15298609
申请日：2016-10-20
Applicant: HRL Laboratories, LLC
Inventor： James Chingwei Li , Yakov Royter , Pamela R. Patterson , Donald A. Hitko
IPC: H01L29/40 , H01L23/48 , H01L29/66 , H01L23/373 , H01L21/683 , H01L29/49 , H01L23/535 , H01L21/74 , H01L21/304 , H01L21/20 , H01L29/737 , H01L33/64 , H01L29/417 , H01L29/45
Abstract: A transistor having an emitter, a base, and a collector, the transistor includes a substrate, a collector contact, a metallic sub-collector coupled to the collector contact, and the metallic sub-collector electrically and thermally coupled to the collector, and an adhesive layer between the substrate and the metallic sub-collector, the adhesive layer bonded to the substrate and in direct contact with the substrate and bonded to the metallic sub-collector and in direct contact with the metallic sub-collector, wherein the adhesive layer comprises an electrically conductive material.
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公开(公告)号：US09843339B1
公开(公告)日：2017-12-12
申请号：US15248358
申请日：2016-08-26
Applicant: HRL Laboratories, LLC
Inventor： Yen-Cheng Kuan , Randall White , Zhiwei A. Xu , Donald A. Hitko , Peter Petre , Jose Cruz-Albrecht , Alan E. Reamon
Abstract: An asynchronous pulse domain to synchronous digital domain converter for converting pulse domain signals in an input asynchronous pulse domain data stream to synchronous digital domain signals in a data output stream. The converter comprises a plurality of counters arranged in a ring configuration with only one counter in the ring being responsive at any given time to positive and negative going pulses in the input asynchronous pulse domain data stream, each counter, when so responsive, counting a number of time units between either (i) a positive going pulse and an immediately following negative going pulse or (ii) a negative going pulse and an immediately following positive going pulse, the counts of the counters when so responsive being synchronously converted to synchronous digital domain signals in the data output stream. The disclosed asynchronous pulse domain to synchronous digital domain converter can be used with spike domain signals if desired.
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公开(公告)号：US09621183B2
公开(公告)日：2017-04-11
申请号：US14745354
申请日：2015-06-19
Applicant: HRL LABORATORIES LLC
Inventor： Cynthia D. Baringer , Zhiwei A. Xu , Peter Petre , Donald A. Hitko , Albert Cosand
Abstract: A delta sigma modulator which has improved the dynamic range. The ΔΣ modulator has a plurality of ADCs and a plurality of DACs, the plurality of ADCs and DACs are connected in a loop. The plurality of ADCs are coupled with an incoming analog signal. A clock generator provides a plurality of clock signals which control the plurality of ADCs and the plurality of DACs, the clock signals being offset relative to each other in the time domain thereby enabling each ADC in the plurality of ADCs one at a time and each DAC in the plurality of DACs one at a time so that the ΔΣ modulator processes data in the incoming analog signal in an interleaved fashion. The delta sigma modulator has an Nth order filter in a forward path of the loop.
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Patent Agency Ranking
公开(公告)号：US09484918B1
公开(公告)日：2016-11-01
申请号：US14834837
申请日：2015-08-25
Applicant: HRL LABORATORIES, LLC
Inventor： Yen-Cheng Kuan , Ining Ku , Zhiwei A. Xu , Susan L. Morton , Donald A. Hitko , Peter Petre , Jose Cruz-Albrecht , Alan E. Reamon
IPC: H03K19/003 , H03K19/00
CPC classification number: H03K19/00369 , H01Q3/26 , H01Q3/2682 , H03K3/86 , H03K19/0016 , H04B7/0617 , H04B7/0671
Abstract: A pulse domain 1 to 2N demultiplexer has a (i) pair of N stage counters each of which is responsive to an incoming pulse train in the pulse domain, one of the counters being responsive to leading edges of the pulses in the incoming pulse train and the other one of the counters being responsive to trailing edges of the pulses in the incoming pulse train and (ii) a control logic responsive to the states through which the pair of counters count, the control logic including 2N gate arrangements, each of the 2N gate arrangements generating a output signal of the pulse domain 1 to 2N demultiplexer.
Abstract translation: 脉冲域1至2N解复用器具有（i）一对N级计数器，每个N级计数器响应于脉冲域中的输入脉冲序列，其中一个计数器响应于输入脉冲串中的脉冲的前沿， 另一个计数器响应输入脉冲串中的脉冲的后沿，以及（ii）响应于该对计数器计数的状态的控制逻辑，包括2N个门装置的控制逻辑，2N个 门结构产生脉冲域1至2N解复用器的输出信号。
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公开(公告)号：US09531571B2
公开(公告)日：2016-12-27
申请号：US14144767
申请日：2013-12-31
Applicant: HRL Laboratories, LLC
Inventor： Zhiwei A. Xu , Yen-Cheng Kuan , James Chingwei Li , Donald A. Hitko , Joseph F. Jensen
CPC classification number: H04L25/08 , H03D7/1441 , H03D7/1458 , H04B1/0035
Abstract: An agile transceiver including a receiver channel that includes an input, a coarse tracking filter coupled to the input, the coarse tracking filter having a set of at least two bandpass filters for filtering signals from the input into at least two coarse pass bands, a mixer coupled to an output of the coarse tracking filter, a selected local oscillator coupled to the mixer for mixing with the output of the coarse tracking filter and shifting a desired coarse pass band to near a base band, a fine tracking filter for filtering the shifted and desired coarse pass band to a fine pass band, and a band pass ΣΔ demodulator for converting signals in the fine pass band from analog into digital. The agile transceiver may include a corresponding transmitter channel.
Abstract translation: 一种敏捷收发器，包括包括输入的接收器通道，耦合到输入的粗跟踪滤波器，粗跟踪滤波器具有一组至少两个带通滤波器，用于将来自输入的信号滤波成至少两个粗通带;混频器 耦合到粗跟踪滤波器的输出，耦合到混频器的选定的本地振荡器，用于与粗跟踪滤波器的输出混合并将期望的粗通带移位到基带附近;精细跟踪滤波器，用于滤波偏移和 期望的粗通带到细通带，以及带通ΣΔ解调器，用于将细通带中的信号从模拟转换成数字。 敏捷收发器可以包括相应的发射机信道。
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公开(公告)号：US10361731B2
公开(公告)日：2019-07-23
申请号：US15828106
申请日：2017-11-30
Applicant: HRL Laboratories, LLC
Inventor： Zhiwei A. Xu , Yen-Cheng Kuan , Cynthia D. Baringer , Hasan Sharifi , James Chingwei Li , Donald A. Hitko
Abstract: A Delta-Sigma modulator architecture is disclosed that uses interleaving and dynamic matching algorithms to address the needs of multi-mode, multi-band high bandwidth transmitters. The proposed architecture also supports a novel software defined transmitter architecture based on an interleaved Delta-Sigma modulator to generate RF signals. The proposed architecture leverages interleaving concepts to relax subcomponent clock rates without changing the effective oversampling ratio, thus, making it easier to reach aggressive dynamic range goals across wider bandwidths at higher frequencies. The DEM algorithm helps to randomize mismatch errors across all interleaved paths and improves substantially the signal-to-noise ratio. Additionally, a tunable bandpass filter can be added to reject out-of-band emissions.
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公开(公告)号：US20190165820A1
公开(公告)日：2019-05-30
申请号：US15828106
申请日：2017-11-30
Applicant: HRL Laboratories, LLC
Inventor： Zhiwei A. Xu , Yen-Cheng Kuan , Cynthia D. Baringer , Hasan Sharifi , James Chingwei Li , Donald A. Hitko
Abstract: A Delta-Sigma modulator architecture is disclosed that uses interleaving and dynamic matching algorithms to address the needs of multi-mode, multi-band high bandwidth transmitters. The proposed architecture also supports a novel software defined transmitter architecture based on an interleaved Delta-Sigma modulator to generate RF signals. The proposed architecture leverages interleaving concepts to relax subcomponent clock rates without changing the effective oversampling ratio, thus, making it easier to reach aggressive dynamic range goals across wider bandwidths at higher frequencies. The DEM algorithm helps to randomize mismatch errors across all interleaved paths and improves substantially the signal-to-noise ratio. Additionally, a tunable bandpass filter can be added to reject out-of-band emissions.
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公开(公告)号：US20150188737A1
公开(公告)日：2015-07-02
申请号：US14144767
申请日：2013-12-31
Applicant: HRL Laboratories, LLC
Inventor： Zhiwei A. XU , Yen-Cheng Kuan , James Chingwei Li , Donald A. Hitko , Joseph F. Jensen
CPC classification number: H04L25/08 , H03D7/1441 , H03D7/1458 , H04B1/0035
Abstract: An agile transceiver including a receiver channel that includes an input, a coarse tracking filter coupled to the input, the coarse tracking filter having a set of at least two bandpass filters for filtering signals from the input into at least two coarse pass bands, a mixer coupled to an output of the coarse tracking filter, a selected local oscillator coupled to the mixer for mixing with the output of the coarse tracking filter and shifting a desired coarse pass band to near a base band, a fine tracking filter for filtering the shifted and desired coarse pass band to a fine pass band, and a band pass ΣΔ demodulator for converting signals in the fine pass band from analog into digital. The agile transceiver may include a corresponding transmitter channel.
Abstract translation: 一种敏捷收发器，包括包括输入的接收器通道，耦合到输入的粗跟踪滤波器，粗跟踪滤波器具有一组至少两个带通滤波器，用于将来自输入的信号滤波成至少两个粗通带;混频器 耦合到粗跟踪滤波器的输出，耦合到混频器的选定的本地振荡器，用于与粗跟踪滤波器的输出混合并将期望的粗通带移位到基带附近;精细跟踪滤波器，用于滤波偏移和 期望的粗通带到细通带，带通＆amp; Dgr; 解调器，用于将细通带中的信号从模拟转换成数字。 敏捷收发器可以包括相应的发射机信道。
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