公开(公告)号：US09621183B2

公开(公告)日：2017-04-11

申请号：US14745354

申请日：2015-06-19

申请人： HRL LABORATORIES LLC

发明人： Cynthia D. Baringer ,  Zhiwei A. Xu ,  Peter Petre ,  Donald A. Hitko ,  Albert Cosand

IPC分类号： H03M3/00 ,  H03M1/06

CPC分类号： H03M3/47 ,  H03M1/066 ,  H03M3/358 ,  H03M3/37 ,  H03M3/454 ,  H03M3/46

摘要： A delta sigma modulator which has improved the dynamic range. The ΔΣ modulator has a plurality of ADCs and a plurality of DACs, the plurality of ADCs and DACs are connected in a loop. The plurality of ADCs are coupled with an incoming analog signal. A clock generator provides a plurality of clock signals which control the plurality of ADCs and the plurality of DACs, the clock signals being offset relative to each other in the time domain thereby enabling each ADC in the plurality of ADCs one at a time and each DAC in the plurality of DACs one at a time so that the ΔΣ modulator processes data in the incoming analog signal in an interleaved fashion. The delta sigma modulator has an Nth order filter in a forward path of the loop.