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1.发明申请公开(公告)号：US20190158111A1
公开(公告)日：2019-05-23
申请号：US16134960
申请日：2018-09-18
申请人： MEDIATEK INC.
发明人： Hung-Yi Hsieh
IPC分类号： H03M3/00
CPC分类号： H03M3/342 , H03M1/145 , H03M1/164 , H03M3/344 , H03M3/424 , H03M3/426 , H03M3/428 , H03M3/436 , H03M3/47
摘要： The present invention provides a continuous-time delta-sigma modulator comprising two ADCs. One of the ADC is configured to generate MSBs of an output signal of the continuous-time delta-sigma modulator, and the other ADC is configured to generate LSBs of the output signal. In addition, the two ADCs sample an output of a loop filter at different times, but the MSBs and LSBs are feedback to the loop filter simultaneously.
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公开(公告)号：US20180175875A1
公开(公告)日：2018-06-21
申请号：US15603546
申请日：2017-05-24
申请人： MEDIATEK Inc.
发明人： Jen-Huan Tsai
CPC分类号： H03M1/1245 , H03M1/0626 , H03M1/468 , H03M3/426 , H03M3/458 , H03M3/47
摘要： The invention provides an analog-to-digital converter (ADC) converting an input signal to an output signal. The ADC may comprise a main circuit and a comparator coupled to the main circuit. The main circuit may: transfer the input signal by an input transfer block, filter an error signal by a loop filter, and combine the transferred input signal and the filtered error signal to form a combined signal. The comparator may quantize the combined signal to provide the output signal, wherein the error signal may reflect a difference between the combined signal and the output signal.
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公开(公告)号：US09621183B2
公开(公告)日：2017-04-11
申请号：US14745354
申请日：2015-06-19
申请人： HRL LABORATORIES LLC
摘要： A delta sigma modulator which has improved the dynamic range. The ΔΣ modulator has a plurality of ADCs and a plurality of DACs, the plurality of ADCs and DACs are connected in a loop. The plurality of ADCs are coupled with an incoming analog signal. A clock generator provides a plurality of clock signals which control the plurality of ADCs and the plurality of DACs, the clock signals being offset relative to each other in the time domain thereby enabling each ADC in the plurality of ADCs one at a time and each DAC in the plurality of DACs one at a time so that the ΔΣ modulator processes data in the incoming analog signal in an interleaved fashion. The delta sigma modulator has an Nth order filter in a forward path of the loop.
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公开(公告)号：US09197242B2
公开(公告)日：2015-11-24
申请号：US14559176
申请日：2014-12-03
发明人： Lasse Aaltonen , Teemu Salo , Tero Sillanpää
IPC分类号： H03M3/00
摘要： A delta-sigma analog-to-digital converter for use with multiplexed input channels. The delta-sigma analog-to-digital converter comprising at least one integrator that includes an operational amplifier, a memory element with a leakage preventing switch structure for each input channel and a reset switch element adapted to reset the operational amplifier between the input channels. The specific switch design prevents effectively channel to channel cross talk between multiplexed channels.
摘要翻译： 用于复用输入通道的delta-sigma模数转换器。 Δ-Σ模数转换器包括至少一个积分器，其包括运算放大器，具有用于每个输入通道的防漏开关结构的存储器元件和适于在输入通道之间复位运算放大器的复位开关元件。 具体的开关设计有效地阻止了多路复用通道之间的通道串扰。
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公开(公告)号：US20140266820A1
公开(公告)日：2014-09-18
申请号：US14184334
申请日：2014-02-19
申请人： LSI Corporation
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03F3/217 , H03F2200/331 , H03H17/0018 , H03H17/0273 , H03H17/028 , H03M3/30 , H03M3/37 , H03M3/47 , H04L25/02 , H04L27/02
摘要： In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit-stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects.
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公开(公告)号：US08779958B1
公开(公告)日：2014-07-15
申请号：US13747241
申请日：2013-01-22
摘要： A continuous time input stage including a first digital-to-analog converter (DAC) including a first DAC code input, a second DAC including a second DAC code input, a first set of switches coupled to the output of the first DAC, a second set of switches coupled to the output of the second DAC, and an amplifier configured to receive the output of either the first DAC or the second DAC.
摘要翻译： 连续时间输入级包括包括第一DAC代码输入的第一数模转换器（DAC），包括第二DAC代码输入的第二DAC，耦合到第一DAC的输出的第一组开关，第二DAC 耦合到第二DAC的输出的开关组以及被配置为接收第一DAC或第二DAC的输出的放大器。
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7.发明申请ELECTRONIC DEVICE AND METHOD FOR ANALOG TO DIGITAL CONVERSION ACCORDING TO DELTA-SIGMA MODULATION USING DOUBLE SAMPLING 有权电子装置和方法，用于使用双重采样对数字转换进行三角形调制公开(公告)号：US20130278454A1
公开(公告)日：2013-10-24
申请号：US13603179
申请日：2012-09-04
IPC分类号： H03M3/02
摘要： The modulator comprises a first and second integration stages, and a comparator, the first integration stage is fully differential having: an amplifier, sets of input sampling capacitors and feedback capacitors, and the first integration stage is configured to sample the analog input voltage on a set of input capacitors during a first portion of a clock cycle and on a set of input capacitors during a second portion of the clock cycle and to sample the feedback reference voltage on a set of feedback capacitors during the first portion of the clock cycle and on a set of feedback capacitors during the second portion of the clock cycle, and the first set of feedback capacitors and the second set of feedback capacitors are randomly selected out of the plurality of sets of feedback capacitors from cycle to cycle.
摘要翻译： 调制器包括第一和第二积分级和比较器，第一积分级是完全差分的，其具有：放大器，输入采样电容器组和反馈电容器组，并且第一积分级被配置为在模拟输入电压 在时钟周期的第一部分期间的一组输入电容器和在时钟周期的第二部分期间的一组输入电容器，并且在时钟周期的第一部分期间在一组反馈电容器上对反馈参考电压进行采样， 在时钟周期的第二部分期间的一组反馈电容器，以及从周期到周期的多组反馈电容器中随机选择第一组反馈电容器和第二组反馈电容器。
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公开(公告)号：US08472562B2
公开(公告)日：2013-06-25
申请号：US13230660
申请日：2011-09-12
CPC分类号： H04L27/22 , H03M3/462 , H03M3/47 , H03M7/3028 , H04B1/0007
摘要： A receiver and method is provided for sigma-delta converting an RF signal to a digital signal and downconverting to a digital baseband signal. The RF signal is split into N phases, as can be accomplished using a sample and hold circuit, and each phase is digitized, as can be accomplished using an analog-to-digital (A/D) sigma-delta converter. Polyphase decimation techniques and demodulation are applied to the phased signals to generate a demodulated digital signal. The demodulated digital signal is further downconverted to the appropriate baseband signal.
摘要翻译： 提供了一种接收机和方法，用于将RF信号转换成数字信号并下变频成数字基带信号。 RF信号被分为N个相位，可以使用采样和保持电路实现，并且每个相位被数字化，如可以使用模数（A / D）Σ-Δ转换器所实现的。 将多相抽取技术和解调应用于相控信号以产生解调数字信号。 解调的数字信号进一步下变频到适当的基带信号。
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公开(公告)号：US07982646B2
公开(公告)日：2011-07-19
申请号：US12184204
申请日：2008-07-31
IPC分类号： H03M3/00
摘要： A second order superconductor delta-sigma analog-to-digital modulator having an input for receiving an analog signal, a first integrator coupled to the input, a second integrator cascaded with the first integrator, and a quantum comparator digitizing output from the second integrator reduces quantization noise by providing matched quantum accurate DACs in a feedback loop between output from the quantum comparator and input to the first integrator. The matched quantum accurate feedback DACs produce identically repeatable voltage pulses, may be configured for multi-bit output, may be time-interleaved to permit higher clocking rates, and may be employed in a balanced bipolar configuration to allow inductive input coupling. Bipolar feedback is balanced when gain of a first DAC exceeds gain of a matched, opposite polarity DAC by the amount of implicit feedback from the comparator into the second integrator.
摘要翻译： 具有用于接收模拟信号的输入端的第二级超导体Δ-Σ模数转换器，耦合到输入端的第一积分器，与第一积分器级联的第二积分器和来自第二积分器的量子比较器数字化输出减小 通过在量子比较器的输出和第一积分器的输出之间的反馈回路中提供匹配的量子精确DAC来进行量化噪声。 匹配的量子精确反馈DAC产生相同可重复的电压脉冲，可以被配置用于多位输出，可以被时间交织以允许更高的时钟速率，并且可以采用平衡双极配置来允许电感输入耦合。 当第一个DAC的增益超过匹配的相反极性DAC的增益时，双极反馈被平衡，这是由比较器到第二个积分器的隐含反馈量。
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公开(公告)号：US07242333B1
公开(公告)日：2007-07-10
申请号：US11323834
申请日：2005-12-30
申请人： Jin-Yong Wu
发明人： Jin-Yong Wu
IPC分类号： H03M1/00
摘要： An alternate sampling integrator circuit is disclosed that can concurrently sample and integrate signals received at an input. The circuit may include multiple sampling capacitors, an operational amplifier, and multiple switches. The switches switch the capacitors between a sampling mode and an integration mode.
摘要翻译： 公开了一种替代采样积分器电路，其可以同时采样和积分在输入端接收的信号。 电路可以包括多个采样电容器，运算放大器和多个开关。 开关在采样模式和积分模式之间切换电容器。
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