公开(公告)号：US20210390994A1

公开(公告)日：2021-12-16

申请号：US17412904

申请日：2021-08-26

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Jeffrey Junhao XU ,  Huan YANG ,  Riqing ZHANG

IPC: G11C11/16 ,  H01L43/02 ,  H01L27/22 ,  H01L43/10

Abstract: This application provides a magneto-resistive random access memory, to reduce a chip area. The magneto-resistive random access memory includes: a plurality of stacked stacking layers, where each stacking layer includes a plurality of magnetic memory cells arranged in a two-dimensional manner; and a plurality of selective metal layers, where each stacking layer is disposed between two selective metal layers and is adjacent to the two selective metal layers, and each selective metal layer is connected to a magnetic memory cell in an adjacent stacking layer, and is configured to perform a read/write operation on the magnetic memory cell.

公开(公告)号：US20250046356A1

公开(公告)日：2025-02-06

申请号：US18921132

申请日：2024-10-21

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Jeffrey Junhao XU ,  Huan YANG ,  Riqing ZHANG

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

Abstract: This application provides a magneto-resistive random access memory, to reduce a chip area. The magneto-resistive random access memory includes: a plurality of stacked stacking layers, where each stacking layer includes a plurality of magnetic memory cells arranged in a two-dimensional manner; and a plurality of selective metal layers, where each stacking layer is disposed between two selective metal layers and is adjacent to the two selective metal layers, and each selective metal layer is connected to a magnetic memory cell in an adjacent stacking layer, and is configured to perform a read/write operation on the magnetic memory cell.

公开(公告)号：US20250040147A1

公开(公告)日：2025-01-30

申请号：US18918918

申请日：2024-10-17

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Wanliang TAN ,  Sheng ZENG ,  Hangbing LV ,  Jeffrey Junhao XU

IPC: H10B53/30 ,  H10B53/20

Abstract: Embodiments of this disclosure relate to the field of semiconductor technologies, and disclose example memories and example preparation methods therefor, and example electronic devices. One example memory includes a first laminated structure, a first passivation part, a functional layer, a first passivation layer, and a second conductive layer. The first laminated structure has a first hole that penetrates the first laminated structure, and the first laminated structure includes a plurality of first conductive layers that are stacked. The first passivation part is located in a first conductive layer of the plurality of first conductive layers and is at a same layer as the first conductive layer. In addition, the first passivation part encircles the first hole, and a material of the first passivation part is oxide of a material of the first conductive layer.

公开(公告)号：US20250069634A1

公开(公告)日：2025-02-27

申请号：US18948981

申请日：2024-11-15

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Wanliang TAN ,  Jialin CAI ,  Jeffrey Junhao XU

IPC: G11C11/22

Abstract: Examples of a ferroelectric memory, a control apparatus, and a method for increasing endurance of the ferroelectric memory are described. One example control apparatus of the ferroelectric memory includes a signal control device. The signal control device is coupled to a memory controller, an alternating current signal generator, and a plate line coupled to a ferroelectric memory cell. The signal control device is configured to switch a signal inputted to the plate line to a first alternating current signal generated by the alternating current signal generator or a read/write pulse signal outputted by the memory controller. In some examples, the signal control device is configured to superimpose a second alternating current signal generated by the alternating current signal generator and the read/write pulse signal, and input a superimposed signal to the plate line.

公开(公告)号：US20230276636A1

公开(公告)日：2023-08-31

申请号：US18311598

申请日：2023-05-03

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Jeffrey Junhao XU ,  Weiliang JING ,  Sitong BU ,  Yichen FANG ,  Ying WU ,  Zhaozhao HOU ,  Wanliang TAN ,  Heng ZHANG ,  Yu ZHANG

IPC: H10B53/30 ,  H10B53/20

CPC classification number: H10B53/30 ,  H10B53/20

Abstract: Example ferroelectric memories and storage devices are described One example ferroelectric memory includes at least one bit cell. A bit cell in the at least one bit cell includes a plurality of ferroelectric capacitors and a first transistor. The first transistor includes a first gate, a first channel, a first source, and a first drain. The first source and the first drain are located at two ends of the first channel. One electrode of each of the plurality of ferroelectric capacitors is formed on the first gate.