公开(公告)号：US20230325276A1

公开(公告)日：2023-10-12

申请号：US18327374

申请日：2023-06-01

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yuwei LI ,  Xu ZHANG ,  Wei LI ,  Kun ZHANG ,  Wen YIN

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/0787 ,  G06F11/0793

Abstract: Example error correction methods and apparatus are described. In one example method, a register controller detects an error existing in a memory, and after detecting an uncorrected error (UCE), obtains a memory address in which the UCE occurs. The register controller reads raw data from a location indicated by the memory address, stores preset first data in the location indicated by the memory address, and reads second data from the location after storing the first data in the location. The register controller compares the first data with the second data to determine a first failure location in the location, determines raw data stored in the first failure location from the raw data in the location, and performs error correction on the raw data stored in the first failure location.

公开(公告)号：US20230013151A1

公开(公告)日：2023-01-19

申请号：US17947699

申请日：2022-09-19

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Wen YIN

IPC: G06F1/06 ,  H03L7/08 ,  H01L23/00 ,  H01L23/498

Abstract: A clock circuit constructed in a processor integrated circuit includes a phase lock loop PLL, a clock tree, and a clock grid. The clock tree includes a plurality of clock buffers in a layered structure, The clock tree is configured to receive a first clock signal clk_1 that is output by the phase lock loop PLL, and to output a second clock signal clk_2. A plurality of child node circuits (400) are disposed on some nodes of the clock grid, and are configured to generate a third clock signal clk_3 based on the second clock signal clk_2. The clock grid (330) and the clock tree (320) are distributed on multiple dies in a three-dimensional structure of the processor integrated circuit.