ERROR CORRECTION METHOD AND APPARATUS
    1.
    发明公开

    公开(公告)号:US20230325276A1

    公开(公告)日:2023-10-12

    申请号:US18327374

    申请日:2023-06-01

    CPC classification number: G06F11/1068 G06F11/0787 G06F11/0793

    Abstract: Example error correction methods and apparatus are described. In one example method, a register controller detects an error existing in a memory, and after detecting an uncorrected error (UCE), obtains a memory address in which the UCE occurs. The register controller reads raw data from a location indicated by the memory address, stores preset first data in the location indicated by the memory address, and reads second data from the location after storing the first data in the location. The register controller compares the first data with the second data to determine a first failure location in the location, determines raw data stored in the first failure location from the raw data in the location, and performs error correction on the raw data stored in the first failure location.

    SYNCHRONIZATION INSTRUCTION INSERTION METHOD AND APPARATUS

    公开(公告)号:US20220113971A1

    公开(公告)日:2022-04-14

    申请号:US17558076

    申请日:2021-12-21

    Inventor: Xiong GAO Kun ZHANG

    Abstract: This application discloses example synchronization instruction insertion methods and example apparatuses. One example method includes obtaining a first program block comprising one or more statements, where each of the one or more statements includes one or more function instructions. A first function instruction and a second function instruction between which data dependency exists in the first program block can then be determined. A synchronization instruction pair between a first statement including the first function instruction and a second statement including the second function instruction can then be inserted.

    ANTENNA AND COMMUNICATIONS DEVICE
    3.
    发明申请

    公开(公告)号:US20180248270A1

    公开(公告)日:2018-08-30

    申请号:US15898059

    申请日:2018-02-15

    Abstract: An antenna and a communications device are disclosed. The antenna includes: multiple feeders, a microstrip antenna array, and at least one energy attenuation circuit; the microstrip antenna array includes multiple array elements, where each of the multiple array elements is connected to a cable feeding port by using one of the multiple feeders; each of the at least one energy attenuation circuit is located at a feeder, where the feeder is one of the multiple feeders and is connected to an array element, and the array element is located at a periphery of the multiple array elements; and the energy attenuation circuit includes a resistor, where the resistor is grounded, and the resistor consumes a part of energy in the feeder when the resistor is grounded.

    MANAGEMENT SYSTEM, PROCESSING CHIP, APPARATUS, DEVICE, AND METHOD

    公开(公告)号:US20240045827A1

    公开(公告)日:2024-02-08

    申请号:US18490958

    申请日:2023-10-20

    CPC classification number: G06F13/4282 G06F2213/0026 G06F2213/0042

    Abstract: Example management systems and methods are described. In one example, the management system includes at least one processor and a baseboard management controller (BMC). A data bus used for data transmission is included between the at least one processor and the BMC. The at least one processor is configured to convert a first protocol packet including first management data of the system into a second protocol packet, and send the second protocol packet through the data bus. A protocol type of the second protocol packet is a transmission protocol type of the data bus. A protocol type of the first protocol packet is different from the protocol type of the second protocol packet, and a transmission rate of the first protocol packet is lower than a transmission rate of the second protocol packet.

Patent Agency Ranking