公开(公告)号：US10042560B2

公开(公告)日：2018-08-07

申请号：US15449027

申请日：2017-03-03

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Wei Zhang ,  Xianhong Lu ,  Mingchang Wei ,  Chenyi Zhang

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0871

Abstract: According to a write data request processing method and a storage array provided in the embodiments of the present invention, a controller is connected to a cache device via a switching device, an input/output manager is connected to the controller via the switching device, and the input/output manager is connected to a cache device via the switching device. The controller obtains a cache address from the cache device for to-be-written data according to the write data request, the controller sends an identifier of the cache device and the cache address to the input/output manager via the switching device, and the input/output manager writes the to-be-written data to the cache address via the switching device.

公开(公告)号：US10203899B2

公开(公告)日：2019-02-12

申请号：US14979000

申请日：2015-12-22

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Chenyi Zhang ,  Chungong Lin ,  Mingchang Wei

IPC: G06F3/06 ,  G06F12/02

Abstract: A flash memory apparatus for controlling storage of data comprises a plurality of blocks for storing data and a controller. Each block includes a plurality of pages. The controller receives first target data and identifies a first block to store the first target data. Then, the controller divides the first target data into two parts. A size of a first part is equal to the available capacity of the first block. And a size of a second part is equal to the size of the first target data minus the size of the first part. The controller further determines a second block that has stored data but is not full. At last, the controller writes the first part into the first block and write the second part into the second block.

公开(公告)号：US20160110107A1

公开(公告)日：2016-04-21

申请号：US14979000

申请日：2015-12-22

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Chenyi Zhang ,  Chungong Lin ,  Mingchang Wei

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1032 ,  G06F2212/1044 ,  G06F2212/7204

Abstract: A flash memory apparatus for controlling storage of data comprises a plurality of blocks for storing data and a controller. Each block includes a plurality of pages. The controller receives first target data and identifies a first block to store the first target data. Then, the controller divides the first target data into two parts. A size of a first part is equal to the available capacity of the first block. And a size of a second part is equal to the size of the first target data minus the size of the first part. The controller further determines a second block that has stored data but is not full. At last, the controller writes the first part into the first block and write the second part into the second block.

Abstract translation: 用于控制数据存储的闪速存储装置包括用于存储数据的多个块和控制器。 每个块包括多个页面。 控制器接收第一目标数据并识别第一块以存储第一目标数据。 然后，控制器将第一目标数据分成两部分。 第一部分的尺寸等于第一块的可用容量。 并且第二部分的大小等于第一目标数据的大小减去第一部分的大小。 控制器进一步确定存储数据但不满的第二块。 最后，控制器将第一部分写入第一个块，并将第二个部分写入第二个块。

公开(公告)号：US20150378888A1

公开(公告)日：2015-12-31

申请号：US14719844

申请日：2015-05-22

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Chenyi Zhang ,  Chungong Lin ,  Mingchang Wei

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/0868 ,  G06F2212/1032 ,  G06F2212/214 ,  G06F2212/7204 ,  G06F2212/7208 ,  G06F2212/7209 ,  G11C29/883

Abstract: A storage controller for determining an amount of data to be sent to a flash memory apparatus for storage comprises a communications interface for communicating with the flash memory apparatus and a processor. The flash memory apparatus comprises a block including a plurality of pages. And at least one of the pages is unavailable for storage. The processor is configured to receive information of the block sent by the flash memory apparatus, wherein the information includes capacity of one or more unavailable pages in the block. And then, the processor determines an available capacity of the block, based on the information and a total capacity of the block. Further, the processor obtains data to be sent to the flash memory apparatus, wherein an amount of the data is equal to the available capacity of the block. At last, the processor sends the data to the flash memory apparatus.

Abstract translation: 用于确定要发送到用于存储的闪存设备的数据量的存储控制器包括用于与闪存设备和处理器进行通信的通信接口。 闪存装置包括包括多页的块。 并且至少有一个页面不可用于存储。 处理器被配置为接收由闪存设备发送的块的信息，其中该信息包括该块中的一个或多个不可用页面的容量。 然后，处理器基于块的信息和总容量确定块的可用容量。 此外，处理器获得要发送到闪存设备的数据，其中数据量等于块的可用容量。 最后，处理器将数据发送到闪存装置。

公开(公告)号：US20180321846A1

公开(公告)日：2018-11-08

申请号：US16034078

申请日：2018-07-12

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Wei Zhang ,  Xianhong Lu ,  Mingchang Wei ,  Chenyi Zhang

IPC: G06F3/06 ,  G06F12/0871

CPC classification number: G06F3/061 ,  G06F3/06 ,  G06F3/0619 ,  G06F3/0638 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0871 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/261 ,  G06F2212/604

Abstract: According to a write data request processing method and a storage array provided in the embodiments of the present invention, a controller is connected to a cache device via a switching device, an input/output manager is connected to the controller via the switching device, and the input/output manager is connected to a cache device via the switching device. The controller obtains a cache address from the cache device for to-be-written data according to the write data request, the controller sends an identifier of the cache device and the cache address to the input/output manager via the switching device, and the input/output manager writes the to-be-written data to the cache address via the switching device.

公开(公告)号：US20170177489A1

公开(公告)日：2017-06-22

申请号：US15449083

申请日：2017-03-03

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Wei Zhang ,  Xianhong Lu ,  Mingchang Wei ,  Chenyi Zhang

IPC: G06F12/0891

CPC classification number: G06F12/0891 ,  G06F3/06 ,  G06F3/0608 ,  G06F3/0641 ,  G06F3/067 ,  G06F2212/1044

Abstract: According to a data deduplication system and method for a storage array is provided in embodiments of the present invention, where a controller is connected to a cache device via a switching device, the cache device calculates an eigenvalue of a to-be-deduplicated data block, the controller queries an eigenvalue index set of data blocks according to the eigenvalue of the to-be-deduplicated data block, and when the same eigenvalue is not found, the controller sends a cache address of the to-be-deduplicated data block in the cache device to a controller of a target storage unit such as a hard disk drive, and the controller of the target hard disk reads the to-be-deduplicated data block from the cache address of the data block.

公开(公告)号：US20170177223A1

公开(公告)日：2017-06-22

申请号：US15449027

申请日：2017-03-03

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Wei Zhang ,  Xianhong Lu ,  Mingchang Wei ,  Chenyi Zhang

IPC: G06F3/06 ,  G06F12/0871

CPC classification number: G06F3/061 ,  G06F3/06 ,  G06F3/0619 ,  G06F3/0638 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0871 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/261 ,  G06F2212/604

Abstract: According to a write data request processing method and a storage array provided in the embodiments of the present invention, a controller is connected to a cache device via a switching device, an input/output manager is connected to the controller via the switching device, and the input/output manager is connected to a cache device via the switching device. The controller obtains a cache address from the cache device for to-be-written data according to the write data request, the controller sends an identifier of the cache device and the cache address to the input/output manager via the switching device, and the input/output manager writes the to-be-written data to the cache address via the switching device.