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公开(公告)号:US10319851B2
公开(公告)日:2019-06-11
申请号:US15377708
申请日:2016-12-13
Applicant: Hyundai Motor Company
Inventor: Dae Hwan Chun , Youngkyun Jung , NackYong Joo , Junghee Park , JongSeok Lee
IPC: H01L29/78 , H01L21/265 , H01L21/306 , H01L29/16 , H01L29/423 , H01L29/66 , H01L21/033
Abstract: A semiconductor device includes an n+ type silicon carbide substrate, an n− type layer, an n type layer, a plurality of trenches, a p type region, an n+ type region, a gate insulating film, a gate electrode, a source electrode, a drain electrode, and a channel. The plurality of trenches is disposed in a planar matrix shape. The n+ type region is disposed in a planar mesh type with openings, surrounds each of the trenches, and is in contact with the source electrode between the trenches adjacent to each other in a planar diagonal direction. The p type region is disposed in the opening of the n+ type region in a planar mesh type.
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公开(公告)号:US10121863B2
公开(公告)日:2018-11-06
申请号:US15631993
申请日:2017-06-23
Applicant: Hyundai Motor Company , Kia Motors Corporation
Inventor: NackYong Joo , Youngkyun Jung , Junghee Park , JongSeok Lee , Dae Hwan Chun
IPC: H01L29/16 , H01L29/66 , H01L29/78 , H01L29/423
Abstract: A semiconductor device may include an n− type layer sequentially disposed at a first surface of an n+ type silicon carbide substrate; a p type region disposed in the n− type layer; an auxiliary n+ type region disposed on the p type region or in the p type region; an n+ type region disposed in the p type region; an auxiliary electrode disposed on the auxiliary n+ type region and the p type region; a gate electrode separated from the auxiliary electrode and disposed on the n− type layer; a source electrode separated from the auxiliary electrode and the gate electrode; and a drain electrode disposed at a second surface of the n+ type silicon carbide substrate, wherein the auxiliary n+ type region and the n+ type region are separated from each other, and the source electrode is in contact with the n+ type region.
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公开(公告)号:US09865701B2
公开(公告)日:2018-01-09
申请号:US15440657
申请日:2017-02-23
Applicant: Hyundai Motor Company
Inventor: Youngkyun Jung , Junghee Park , Dae Hwan Chun , JongSeok Lee
IPC: H01L29/66 , H01L29/16 , H01L21/02 , H01L29/872 , H01L23/535 , H01L21/768 , H01L21/265 , H01L21/306
CPC classification number: H01L29/66143 , H01L21/02529 , H01L21/26506 , H01L21/30604 , H01L21/76895 , H01L23/535 , H01L29/0623 , H01L29/1608 , H01L29/6606 , H01L29/872
Abstract: A Schottky barrier diode includes: an n+ type of silicon carbide substrate; an n− type of epitaxial layer formed on a first surface of the n+ type of silicon carbide substrate; a plurality of p+ regions formed inside the n− type of epitaxial layer; a Schottky electrode formed in an upper portion of the n− type of epitaxial layer of an electrode region; and an ohmic electrode formed on a second surface of the n+ type of silicon carbide substrate, wherein the plurality of p+ regions are formed to be spaced apart from each other at a predetermined interval within the n− type of epitaxial layer.
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公开(公告)号:US09391167B1
公开(公告)日:2016-07-12
申请号:US14944950
申请日:2015-11-18
Applicant: Hyundai Motor Company
Inventor: Youngkyun Jung , Junghee Park , Dae Hwan Chun , JongSeok Lee
IPC: H01L21/336 , H01L29/66 , H01L29/16 , H01L29/417
CPC classification number: H01L29/66734 , H01L21/0465 , H01L21/047 , H01L29/0619 , H01L29/1608 , H01L29/41766 , H01L29/4236
Abstract: A method for manufacturing a semiconductor device includes: forming sequentially an n− type epitaxial layer and an n+ type area on a first surface of an n+ type silicon carbide substrate; forming a plurality of first trenches and a plurality of second trenches by etching the n− type epitaxial layer and the n+ type area using a first mask pattern as a mask after forming the first mask pattern on the n+ type area; forming a groove by etching the first mask pattern using a first photosensitive film pattern as a mask after forming the first photosensitive film pattern in the plurality of first trenches; forming a p type area by injecting p ions in the plurality of second trenches using the first mask pattern with the groove as the mask after removing the first photosensitive film pattern; forming a gate insulating layer in the plurality of first trenches after removing the first mask pattern with the groove; forming a gate electrode on the gate insulating layer; forming a passivation layer on the gate electrode; forming a source electrode in the plurality of second trenches; and forming a drain electrode on a second surface which is an opposite side to the first surface of the n+ type silicon carbide substrate.
Abstract translation: 一种制造半导体器件的方法包括:在n +型碳化硅衬底的第一表面上依次形成n型外延层和n +型区域; 通过在n +型区域上形成第一掩模图案之后,使用第一掩模图案作为掩模蚀刻n型外延层和n +型区域,形成多个第一沟槽和多个第二沟槽; 通过在所述多个第一沟槽中形成所述第一感光膜图案之后,使用第一感光膜图案作为掩模蚀刻所述第一掩模图案来形成沟槽; 通过在去除第一感光膜图案之后,使用具有沟槽作为掩模的第一掩模图案,在多个第二沟槽中注入p离子来形成p型区域; 在用所述槽除去所述第一掩模图案之后,在所述多个第一沟槽中形成栅极绝缘层; 在栅极绝缘层上形成栅电极; 在栅电极上形成钝化层; 在所述多个第二沟槽中形成源电极; 以及在与n +型碳化硅衬底的第一表面相反的一侧的第二表面上形成漏电极。
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公开(公告)号:US11735653B2
公开(公告)日:2023-08-22
申请号:US17170995
申请日:2021-02-09
Applicant: Hyundai Motor Company , KIA Motors Corporation
Inventor: JongSeok Lee
IPC: H01L29/78 , H01L29/10 , H01L29/423
CPC classification number: H01L29/7813 , H01L29/1033 , H01L29/1095 , H01L29/4236
Abstract: An exemplary semiconductor device may include a substrate, an N− epitaxial layer positioned on the substrate, a first P region and a second P region positioned apart from each other on the N− epitaxial layer, a first N+ region positioned within the first P region, a second N+ region positioned within the second P region, and a gate layer positioned between the first P region and the second P region.
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6.
公开(公告)号:US20190123171A1
公开(公告)日:2019-04-25
申请号:US15823856
申请日:2017-11-28
Applicant: Hyundai Motor Company , Kia Motors Corporation
Inventor: Youngkyun Jung , NackYong Joo , Junghee Park , Hyun Woo Noh , JongSeok Lee , Dae Hwan Chun
IPC: H01L29/66 , H01L29/423 , H01L21/3065 , H01L21/308
Abstract: A manufacturing method of a semiconductor device is provided. The method includes sequentially forming an n− type of layer, a p type of region, and an n+ type of region on a first surface of a substrate, forming a preliminary trench in the n− type of layer by a first etching process and forming a preliminary gate insulating layer by a first thermal oxidation process. The method includes etching the lower surface of the preliminary trench and the preliminary second portion to form a trench by a second etching process and forming a gate insulating layer in the trench by a second thermal oxidation process. The gate insulating layer includes a first and second portion. The preliminary first portion is thicker than the preliminary second portion and the first portion. The first portion thickness is equal to the thickness of the second portion.
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公开(公告)号:US20170162665A1
公开(公告)日:2017-06-08
申请号:US15440657
申请日:2017-02-23
Applicant: Hyundai Motor Company
Inventor: Youngkyun Jung , Junghee Park , Dae Hwan Chun , JongSeok Lee
IPC: H01L29/66 , H01L21/02 , H01L21/306 , H01L23/535 , H01L21/768 , H01L21/265 , H01L29/16 , H01L29/872
CPC classification number: H01L29/66143 , H01L21/02529 , H01L21/26506 , H01L21/30604 , H01L21/76895 , H01L23/535 , H01L29/0623 , H01L29/1608 , H01L29/6606 , H01L29/872
Abstract: A Schottky barrier diode includes: an n+ type of silicon carbide substrate; an n− type of epitaxial layer formed on a first surface of the n+ type of silicon carbide substrate; a plurality of p+ regions formed inside the n− type of epitaxial layer; a Schottky electrode formed in an upper portion of the n− type of epitaxial layer of an electrode region; and an ohmic electrode formed on a second surface of the n+ type of silicon carbide substrate, wherein the plurality of p+ regions are formed to be spaced apart from each other at a predetermined interval within the n− type of epitaxial layer.
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8.
公开(公告)号:US20170033240A1
公开(公告)日:2017-02-02
申请号:US14952186
申请日:2015-11-25
Applicant: Hyundai Motor Company
Inventor: Youngkyun Jung , Junghee Park , Dae Hwan Chun , JongSeok Lee
IPC: H01L29/872 , H01L21/266 , H01L29/45 , H01L21/265 , H01L29/16 , H01L29/66
CPC classification number: H01L29/66143 , H01L21/02529 , H01L21/26506 , H01L21/30604 , H01L21/76895 , H01L23/535 , H01L29/0623 , H01L29/1608 , H01L29/6606 , H01L29/872
Abstract: A Schottky barrier diode includes: an n+ type of silicon carbide substrate; an n-type of epitaxial layer formed on a first surface of the n+ type of silicon carbide substrate; a plurality of p+ regions formed inside the n-type of epitaxial layer; a Schottky electrode formed in an upper portion of the n-type of epitaxial layer of an electrode region; and an ohmic electrode formed on a second surface of the n+ type of silicon carbide substrate, wherein the plurality of p+ regions are formed to be spaced apart from each other at a predetermined interval within the n-type of epitaxial layer.
Abstract translation: 肖特基势垒二极管包括:n +型碳化硅衬底; 在n +型碳化硅衬底的第一表面上形成的n型外延层; 形成在n型外延层内的多个p +区; 形成在电极区域的n型外延层的上部的肖特基电极; 以及形成在所述n +型碳化硅衬底的第二表面上的欧姆电极,其中所述多个p +区形成为在所述n型外延层内以预定间隔彼此间隔开。
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公开(公告)号:US20220157987A1
公开(公告)日:2022-05-19
申请号:US17170995
申请日:2021-02-09
Applicant: Hyundai Motor Company , KIA Motors Corporation
Inventor: JongSeok Lee
IPC: H01L29/78 , H01L29/10 , H01L29/423
Abstract: An exemplary semiconductor device may include a substrate, an N− epitaxial layer positioned on the substrate, a first P region and a second P region positioned apart from each other on the N− epitaxial layer, a first N+ region positioned within the first P region, a second N+ region positioned within the second P region, and a gate layer positioned between the first P region and the second P region.
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公开(公告)号:US20190341504A1
公开(公告)日:2019-11-07
申请号:US16165885
申请日:2018-10-19
Applicant: Hyundai Motor Company , Kia Motors Corporation
Inventor: NackYong Joo , Youngkyun Jung , Junghee Park , JongSeok Lee , Dae Hwan Chun
IPC: H01L29/872 , H01L29/06 , H01L29/08 , H01L29/47
Abstract: A semiconductor device may include an n− type of layer disposed at a first surface of a substrate; a p− type of region and a p+ type of region disposed at a top portion of the n− type of layer; a first electrode disposed on the p− type of region and the p+ type of region; and a second electrode disposed at a second surface of the substrate, wherein the first electrode includes a first metal layer disposed on the p− type of region and a second metal layer disposed on the first metal layer, and the first metal layer is in continuous contact with the p− type of region.
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