Semiconductor device and method of manufacturing the same

    公开(公告)号:US12224341B2

    公开(公告)日:2025-02-11

    申请号:US17400345

    申请日:2021-08-12

    Inventor: NackYong Joo

    Abstract: A semiconductor device according to an embodiment of the present disclosure includes: a conductive region, an end region positioned at a portion where the conductive region ends, and a connection region positioned between the conductive region and the end region. The conductive region includes: an n+ type substrate; an n− type layer positioned at the first surface of the n+ type substrate; and a p type region positioned on the n− type layer, and a gate electrode that fills an inside of a trench penetrating the p type region and positioned in the n− type layer, and a side wall of the trench positioned at the portion where the conductive region ends is inclined.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20220173241A1

    公开(公告)日:2022-06-02

    申请号:US17400345

    申请日:2021-08-12

    Inventor: NackYong Joo

    Abstract: A semiconductor device according to an embodiment of the present disclosure includes: a conductive region, an end region positioned at a portion where the conductive region ends, and a connection region positioned between the conductive region and the end region. The conductive region includes: an n+ type substrate; an n− type layer positioned at the first surface of the n+ type substrate; and a p type region positioned on the n− type layer, and a gate electrode that fills an inside of a trench penetrating the p type region and positioned in the n− type layer, and a side wall of the trench positioned at the portion where the conductive region ends is inclined.

    Semiconductor device and method manufacturing the same

    公开(公告)号:US10164020B2

    公开(公告)日:2018-12-25

    申请号:US15632077

    申请日:2017-06-23

    Abstract: A semiconductor device may include an n− type layer disposed at a first surface of an n+ type silicon carbide substrate; a p− type region, a p type region, an n+ type region, and a p+ type region disposed at an upper portion in the n− type layer; a gate electrode and a source electrode disposed on the n− type layer and insulated from each other; and a drain electrode disposed at a second surface of the n+ type silicon carbide substrate, wherein the source electrode is in contact with the p− type region, the n+ type region, and the p+ type region, and the source electrode may include an ohmic junction region disposed at a contact portion of the source electrode and the n+ type region and the contact portion of the source region and the p+ type region and a Schottky junction region disposed at the contact portion of the source electrode and the p− type region.

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