Semiconductor device and method of manufacturing the same

    公开(公告)号:US12224341B2

    公开(公告)日:2025-02-11

    申请号:US17400345

    申请日:2021-08-12

    Inventor: NackYong Joo

    Abstract: A semiconductor device according to an embodiment of the present disclosure includes: a conductive region, an end region positioned at a portion where the conductive region ends, and a connection region positioned between the conductive region and the end region. The conductive region includes: an n+ type substrate; an n− type layer positioned at the first surface of the n+ type substrate; and a p type region positioned on the n− type layer, and a gate electrode that fills an inside of a trench penetrating the p type region and positioned in the n− type layer, and a side wall of the trench positioned at the portion where the conductive region ends is inclined.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20220173241A1

    公开(公告)日:2022-06-02

    申请号:US17400345

    申请日:2021-08-12

    Inventor: NackYong Joo

    Abstract: A semiconductor device according to an embodiment of the present disclosure includes: a conductive region, an end region positioned at a portion where the conductive region ends, and a connection region positioned between the conductive region and the end region. The conductive region includes: an n+ type substrate; an n− type layer positioned at the first surface of the n+ type substrate; and a p type region positioned on the n− type layer, and a gate electrode that fills an inside of a trench penetrating the p type region and positioned in the n− type layer, and a side wall of the trench positioned at the portion where the conductive region ends is inclined.

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

    公开(公告)号:US20250022917A1

    公开(公告)日:2025-01-16

    申请号:US18524544

    申请日:2023-11-30

    Abstract: An embodiment semiconductor device includes an N− type layer having a trench therein, a P type region within the N− type layer, an N+ type region within the P type region, a gate electrode within the trench including a first gate electrode having an upper surface lower than an upper surface of the P type region and a second gate electrode having an upper surface lower than the upper surface of the first gate electrode, and source and drain electrodes insulated from the gate electrode, wherein the N+ type region includes a first N+ type region on a side of the first gate electrode and having a lower surface lower than the upper surface of the first gate electrode and a second N+ type region on a side of the second gate electrode and having a lower surface lower than the lower surface of the first N+ type region.

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