公开(公告)号：US20230268419A1

公开(公告)日：2023-08-24

申请号：US17874985

申请日：2022-07-27

申请人： Haitao Liu ,  Naveen Kaushik ,  Chittoor Ranganathan Parthasarathy ,  Deepak Chandra Pandey

发明人： Haitao Liu ,  Naveen Kaushik ,  Chittoor Ranganathan Parthasarathy ,  Deepak Chandra Pandey

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L21/02 ,  H01L21/308

CPC分类号： H01L29/6659 ,  H01L21/0206 ,  H01L21/02293 ,  H01L21/3086 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/16

摘要： A variety of applications can include apparatus having a transistor comprising a modified channel region to address sub-surface leakage issues of the transistor. A dielectric region can be structured to extend from a channel structure of the transistor downward into the substrate for the transistor, with the dielectric region disposed between the source of the transistor and the drain of the transistor to reduce leakage current paths between the source and the drain. The dielectric region can be structured with only dielectric material or with crystalline semiconductor material surrounded by dielectric material.

公开(公告)号：US20220068796A1

公开(公告)日：2022-03-03

申请号：US17461435

申请日：2021-08-30

申请人： Xiaojiang Guo ,  Naveen Kaushik ,  Shuai Xu ,  June Lee

发明人： Xiaojiang Guo ,  Naveen Kaushik ,  Shuai Xu ,  June Lee

IPC分类号： H01L23/522 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

摘要： Memory devices can be structured in a three-dimensional arrangement using a circuit under array (CUA) architecture. The memory array of such a memory device can include memory cells disposed in vertically arranged tiers. With the memory array extending over a substrate, the CUA region under the memory array can include control circuitry for the memory array. A space adjacent the memory array and disposed above the CUA region can include a dielectric material and conductive structures, with the conductive structures extending vertically in the dielectric material and alongside the memory array. The conductive structures separated by the dielectric material can be used as a capacitor coupled between nodes with the nodes configured to provide different voltages. This capacitor can be coupled to a circuit or a connection node below the level of the memory array.