Systems, methods and devices for limiting current consumption by a different ramp rate upon power-up
    1.
    发明授权
    Systems, methods and devices for limiting current consumption by a different ramp rate upon power-up 有权
    用于在上电时以不同的斜坡速率限制电流消耗的系统,方法和设备

    公开(公告)号:US08880920B2

    公开(公告)日:2014-11-04

    申请号:US13078771

    申请日:2011-04-01

    申请人: June Lee

    发明人: June Lee

    IPC分类号: G06F1/00 G11C16/30 G11C5/14

    摘要: Embodiments are described including those for controlling peak current consumption of a multi-chip memory package during power-up. In one embodiment, each memory device of the multi-chip package includes a power level detector used to compare an internal voltage signal to a threshold. A current limiter controls the ramping rate of the internal voltage signal in response to the power level detector as the internal voltage signal ramps up towards the threshold.

    摘要翻译: 描述了实施例,其包括用于在上电期间控制多芯片存储器封装的峰值电流消耗的实施例。 在一个实施例中,多芯片封装的每个存储器件包括用于将内部电压信号与阈值进行比较的功率电平检测器。 当内部电压信号上升到阈值时,电流限制器响应于功率电平检测器来控制内部电压信号的斜坡率。

    Pharmaceutical composition with antibody that binds to heat shock protein 27(HSP270) and method for promoting wound healing
    2.
    发明授权
    Pharmaceutical composition with antibody that binds to heat shock protein 27(HSP270) and method for promoting wound healing 有权
    具有与热休克蛋白27(HSP270)结合的抗体的药物组合物和促进伤口愈合的方法

    公开(公告)号:US08815243B2

    公开(公告)日:2014-08-26

    申请号:US13817760

    申请日:2011-08-18

    摘要: The present invention relates to a pharmaceutical composition for promoting angiogenesis, containing an antibody that specifically binds to heat shock protein (HSP) 27. In addition, the present invention relates to a pharmaceutical composition containing an antibody that specifically binds to HSP 27, for treating an angiogenesis-dependent ailment selected from a group consisting of a wound, chronic ulcer, ischemic stroke, myocardial infarction, angina pectoris, and cerebrovascular dementia. In addition, the present invention relates to a method for promoting the in vitro growth of endothelial cells using an antibody that specifically binds to HSP27. In addition, the present invention relates to a method for screening for active substances for promoting angiogenesis or for active substances for treating an angiogenesis-dependent ailment, the method comprising the following steps: treating vascular endothelial cell lines with each specimen; measuring the content of HSP27 in the respective vascular endothelial cell lines; and selecting a specimen in which the HSP27 content in the vascular endothelial cell lines are decreased as compared to a control group.

    摘要翻译: 本发明涉及用于促进血管生成的药物组合物,其含有与热休克蛋白(HSP)27特异性结合的抗体。此外,本发明涉及含有与HSP27特异性结合的抗体的药物组合物,用于治疗 选自伤口,慢性溃疡,缺血性中风,心肌梗死,心绞痛和脑血管性痴呆的血管发生依赖性疾病。 此外,本发明涉及使用特异性结合HSP27的抗体促进内皮细胞体外生长的方法。 此外,本发明涉及一种筛选用于促进血管发生的活性物质的方法或用于治疗血管生成依赖性疾病的活性物质的方法,所述方法包括以下步骤:用每个样品处理血管内皮细胞系; 测量各血管内皮细胞系中HSP27的含量; 并且与对照组相比,选择其中血管内皮细胞系中HSP27含量降低的标本。

    System and memory for sequential multi-plane page memory operations
    3.
    发明授权
    System and memory for sequential multi-plane page memory operations 有权
    用于顺序多平面页面存储器操作的系统和存储器

    公开(公告)号:US08289802B2

    公开(公告)日:2012-10-16

    申请号:US13051221

    申请日:2011-03-18

    申请人: June Lee

    发明人: June Lee

    IPC分类号: G11C8/00

    摘要: A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory operations are sequentially initiated and the memory operation for at least one of the memory planes is initiated during the memory operation for another memory plane. In one embodiment, each of a plurality of programming circuits is associated with a respective memory plane and is operable to program data to the respective memory plane in response to programming signals and when it is enabled. Control logic coupled to the plurality of programming circuits generates programming signals in response to the memory receiving program commands and further generates programming enable signals to individually enable each of the programming circuits to respond to the programming signals and stagger programming of data to each of the memory planes.

    摘要翻译: 一种用于在多平面闪存中执行存储器操作的系统和方法。 命令和地址被顺序地提供给存储器以用于存储器平面中的存储器操作。 顺序地启动存储器操作,并且在另一存储器平面的存储器操作期间启动至少一个存储器平面的存储器操作。 在一个实施例中,多个编程电路中的每一个与相应的存储器平面相关联,并且可操作以响应于编程信号将数据编程到相应的存储器平面,并且当其被启用时。 耦合到多个编程电路的控制逻辑响应于存储器接收程序命令而产生编程信号,并进一步产生编程使能信号,以单独使编程电路中的每一个能够对编程信号做出响应,并将数据错开编程到每个存储器 飞机

    Methods and control circuitry for programming memory cells
    4.
    发明授权
    Methods and control circuitry for programming memory cells 有权
    用于编程存储器单元的方法和控制电路

    公开(公告)号:US08194450B2

    公开(公告)日:2012-06-05

    申请号:US12815979

    申请日:2010-06-15

    申请人: June Lee

    发明人: June Lee

    IPC分类号: G11C16/00

    摘要: Methods of programming memory cells and control circuitry for memory arrays facilitate a reduction of program disturb. A memory cell is shifted from a first data state to a second data state if it is desired to alter a first digit of a data value of the memory cell. If it is desired to alter a second digit of the data value of the memory cell, the memory cell is shifted to a third data state if the memory cell is in the first data state and shifted to a fourth data state if the memory cell is in the second data state. The first, second, third and fourth data states correspond to respective non-overlapping ranges of threshold voltages. The threshold voltages corresponding to the fourth data state are greater than the threshold voltages corresponding to the third data state.

    摘要翻译: 为存储器阵列编程存储器单元和控制电路的方法有助于减少程序干扰。 如果希望改变存储器单元的数据值的第一位数,则存储单元从第一数据状态转移到第二数据状态。 如果期望改变存储器单元的数据值的第二数位,则如果存储器单元处于第一数据状态并且如果存储器单元是第四数据状态则将存储单元移位到第三数据状态 在第二个数据状态。 第一,第二,第三和第四数据状态对应于阈值电压的相应非重叠范围。 对应于第四数据状态的阈值电压大于对应于第三数据状态的阈值电压。

    HARD DISK CONTROL MODULE, APPARATUSES HAVING THE SAME, AND METHOD OF CONTROLLING UNLOAD STANDBY TIME THEREOF
    5.
    发明申请
    HARD DISK CONTROL MODULE, APPARATUSES HAVING THE SAME, AND METHOD OF CONTROLLING UNLOAD STANDBY TIME THEREOF 审中-公开
    硬盘控制模块,具有该硬盘的装置以及控制其卸载待机时间的方法

    公开(公告)号:US20110242699A1

    公开(公告)日:2011-10-06

    申请号:US13079953

    申请日:2011-04-05

    IPC分类号: G11B21/02

    CPC分类号: G11B21/12

    摘要: A hard disk control module includes a load/unload counter and a controller. The load/unload counter counts a number of loads/unloads of a head on/from a surface of a disk. The controller may determine the number of counted loads/unloads during a reference time. The controller controls an unload standby time of the head according to a load/unload count value and the reference time.

    摘要翻译: 硬盘控制模块包括加载/卸载计数器和控制器。 加载/卸载计数器对磁盘表面上的磁头的加载/卸载进行计数。 控制器可以确定参考时间期间的计数加载/卸载次数。 控制器根据加载/卸载计数值和参考时间控制磁头的卸载待机时间。

    SYSTEMS, METHODS AND DEVICES FOR LIMITING CURRENT CONSUMPTION UPON POWER-UP
    7.
    发明申请
    SYSTEMS, METHODS AND DEVICES FOR LIMITING CURRENT CONSUMPTION UPON POWER-UP 有权
    用于限制上电消耗电流的系统,方法和设备

    公开(公告)号:US20110179296A1

    公开(公告)日:2011-07-21

    申请号:US13078771

    申请日:2011-04-01

    申请人: JUNE LEE

    发明人: JUNE LEE

    IPC分类号: G06F1/32

    摘要: Embodiments are described including those for controlling peak current consumption of a multi-chip memory package during power-up. In one embodiment, each memory device of the multi-chip package includes a power level detector used to compare an internal voltage signal to a threshold. A current limiter controls the ramping rate of the internal voltage signal in response to the power level detector as the internal voltage signal ramps up towards the threshold.

    摘要翻译: 描述了实施例,其包括用于在上电期间控制多芯片存储器封装的峰值电流消耗的实施例。 在一个实施例中,多芯片封装的每个存储器件包括用于将内部电压信号与阈值进行比较的功率电平检测器。 当内部电压信号上升到阈值时,电流限制器响应于功率电平检测器来控制内部电压信号的斜坡率。

    Asynchronous/synchronous interface
    8.
    发明授权
    Asynchronous/synchronous interface 有权
    异步/同步接口

    公开(公告)号:US07920431B2

    公开(公告)日:2011-04-05

    申请号:US12131152

    申请日:2008-06-02

    IPC分类号: G11C7/22

    摘要: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

    摘要翻译: 本公开包括用于操作存储器件的方法和电路。 用于操作存储器件的一个方法实施例包括通过至少部分地响应于第一接口触点上的写入使能信号向存储器件写入数据来控制通过异步模式的存储器接口的数据传输,以及从存储器件读取数据 至少部分地响应于第二接口触点上的读使能信号。 该方法还包括通过至少部分地响应于第一接口触点上的时钟信号传送数据,并且在不在异步模式下使用的接口触点上提供双向数据选通信号,来以同步模式控制数据传输。