公开(公告)号：US20140042524A1

公开(公告)日：2014-02-13

申请号：US13568997

申请日：2012-08-07

申请人： Hak-Lay Chuang ,  Ming Zhu ,  Yi-Ren Chen

发明人： Hak-Lay Chuang ,  Ming Zhu ,  Yi-Ren Chen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L21/28114 ,  H01L21/76885 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823885 ,  H01L29/42376

摘要： A device includes a wafer substrate, a conical frustum structure formed in the wafer substrate, and a gate all-around (GAA) structure circumscribing the middle portion of the conical frustum structure. The conical frustum structure includes a drain formed at a bottom portion of the conical frustum, a source formed at a top portion of the vertical conical frustum, and a channel formed at a middle portion of the conical frustum connecting the source and the drain. The GAA structure overlaps with the source at one side of the GAA structure, crosses over the channel, and overlaps with the drain at another side of the GAA structure.

摘要翻译： 一种器件包括晶片衬底，形成在晶片衬底中的锥形截头锥体结构，以及围绕锥形截头锥体结构的中间部分的栅极全能（GAA）结构。 锥形截头锥体结构包括形成在锥形截头锥体的底部处的排水口，形成在垂直锥形截头锥体的顶部处的源和形成在连接源极和漏极的锥形截头锥体的中间部分处的通道。 GAA结构与GAA结构一侧的源重叠，与沟道交叉，并与GAA结构另一侧的漏极重叠。

公开(公告)号：US08835294B2

公开(公告)日：2014-09-16

申请号：US12724984

申请日：2010-03-16

申请人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang ,  Yi-Ren Chen

发明人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang ,  Yi-Ren Chen

IPC分类号： H01L21/3205 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3215 ,  H01L29/49 ,  H01L21/768 ,  H01L21/8238

CPC分类号： H01L21/28088 ,  H01L21/02697 ,  H01L21/3215 ,  H01L21/76825 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545

摘要： The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure on the substrate, the gate structure including a dummy gate, removing the dummy gate from the gate structure thereby forming a trench, forming a work function metal layer partially filling the trench, forming a fill metal layer filling a remainder of the trench, performing a chemical mechanical polishing (CMP) to remove portions of the metal layers outside the trench, and implanting Si, C, or Ge into a remaining portion of the fill metal layer.

摘要翻译： 本公开提供了一种制造半导体器件的方法，该半导体器件包括提供半导体衬底，在衬底上形成栅极结构，所述栅极结构包括虚拟栅极，从栅极结构去除伪栅极，从而形成沟槽，形成工件 功能金属层部分地填充沟槽，形成填充沟槽的其余部分的填充金属层，执行化学机械抛光（CMP）以去除沟槽外部的金属层，并将Si，C或Ge注入剩余的 填充金属层的一部分。

公开(公告)号：US20110230042A1

公开(公告)日：2011-09-22

申请号：US12724984

申请日：2010-03-16

申请人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang ,  Yi-Ren Chen

发明人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang ,  Yi-Ren Chen

IPC分类号： H01L21/336

CPC分类号： H01L21/28088 ,  H01L21/02697 ,  H01L21/3215 ,  H01L21/76825 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545

摘要： The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure on the substrate, the gate structure including a dummy gate, removing the dummy gate from the gate structure thereby forming a trench, forming a work function metal layer partially filling the trench, forming a fill metal layer filling a remainder of the trench, performing a chemical mechanical polishing (CMP) to remove portions of the metal layers outside the trench, and implanting Si, C, or Ge into a remaining portion of the fill metal layer.

摘要翻译： 本公开提供了一种制造半导体器件的方法，该半导体器件包括提供半导体衬底，在衬底上形成栅极结构，所述栅极结构包括虚拟栅极，从栅极结构去除伪栅极，从而形成沟槽，形成工件 功能金属层部分地填充沟槽，形成填充沟槽的其余部分的填充金属层，执行化学机械抛光（CMP）以去除沟槽外部的金属层，并将Si，C或Ge注入剩余的 填充金属层的一部分。

公开(公告)号：US08742492B2

公开(公告)日：2014-06-03

申请号：US13568997

申请日：2012-08-07

申请人： Hak-Lay Chuang ,  Ming Zhu ,  Yi-Ren Chen

发明人： Hak-Lay Chuang ,  Ming Zhu ,  Yi-Ren Chen

IPC分类号： H01L29/66

CPC分类号： H01L29/66795 ,  H01L21/28114 ,  H01L21/76885 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823885 ,  H01L29/42376

摘要： A device includes a wafer substrate, a conical frustum structure formed in the wafer substrate, and a gate all-around (GAA) structure circumscribing the middle portion of the conical frustum structure. The conical frustum structure includes a drain formed at a bottom portion of the conical frustum, a source formed at a top portion of the vertical conical frustum, and a channel formed at a middle portion of the conical frustum connecting the source and the drain. The GAA structure overlaps with the source at one side of the GAA structure, crosses over the channel, and overlaps with the drain at another side of the GAA structure.

摘要翻译： 一种器件包括晶片衬底，形成在晶片衬底中的锥形截头锥体结构，以及围绕锥形截头锥体结构的中间部分的栅极全能（GAA）结构。 锥形截头锥体结构包括形成在锥形截头锥体的底部处的排水口，形成在垂直锥形截头锥体的顶部处的源和形成在连接源极和漏极的锥形截头锥体的中间部分处的通道。 GAA结构与GAA结构一侧的源重叠，与沟道交叉，并与GAA结构另一侧的漏极重叠。

公开(公告)号：US08166377B2

公开(公告)日：2012-04-24

申请号：US12423897

申请日：2009-04-15

申请人： Yuan-Sun Chu ,  Yi-Ren Chen ,  Chia-Ying Huang ,  Chi-Fang Li

发明人： Yuan-Sun Chu ,  Yi-Ren Chen ,  Chia-Ying Huang ,  Chi-Fang Li

IPC分类号： H03M13/00

CPC分类号： H04L1/0052 ,  H03M13/15 ,  H04L1/0057

摘要： The present invention discloses a configurable hierarchical comma-free Reed-Solomon decoding circuit and a method thereof. The design is based on an original hierarchical parallel architecture which not only completes a decoding process faster than conventional decoder, but also utilizes less hardware to perform various algorithms with less power consumed. The architecture of the present invention has higher decoding rate than the conventional systolic architecture by a cycle ratio of 22 to 94. Further, the present invention does not require the use of ROM to store 64 sets of codewords and uses logic gates less than one fourth of the logic gates than conventional systolic architecture. As a result, the circuit of the present invention occupies less area than the conventional architecture. The circuit of the present invention is also configurable for different applications, so it can always find an optimal compromise between speed and power consumption for various decoding requirements.

摘要翻译： 本发明公开了一种可配置分层无间断里德 - 索罗门解码电路及其方法。 该设计基于原始的分层并行架构，其不仅比传统解码器更快地完成解码过程，而且还利用较少的硬件来执行具有较少功耗的各种算法。 本发明的架构具有比常规收缩结构更高的解码速率，循环比为22至94.此外，本发明不需要使用ROM来存储64组码字，并且使用小于四分之一的逻辑门 的逻辑门比传统的收缩结构。 结果，本发明的电路占用的面积小于常规架构。 本发明的电路也可以针对不同的应用进行配置，因此它可以总是在各种解码要求之间找到速度和功耗之间的最佳折中。

公开(公告)号：US08000352B2

公开(公告)日：2011-08-16

申请号：US12419911

申请日：2009-04-07

申请人： Yuan-Sun Chu ,  Ting-Huan Li ,  Yi-Ren Chen ,  Chia-Ying Huang ,  Kuo-Hua Pu ,  Chi-Fang Li

发明人： Yuan-Sun Chu ,  Ting-Huan Li ,  Yi-Ren Chen ,  Chia-Ying Huang ,  Kuo-Hua Pu ,  Chi-Fang Li

IPC分类号： H04J3/06

CPC分类号： H04W56/00 ,  H04B1/7075 ,  H04B2201/70707 ,  H04W92/10

摘要： A synchronizer for a communication device and an access point, which is installed inside the communication device and comprises a coefficient generator generating a set of coefficient code. A parallel-to-serial converter receives a set of input code from an access point, performs a parallel-to-serial conversion on the set of input code and outputs a result. A coefficient element array includes a plurality of coefficient elements interconnecting with each other. Each of the coefficient elements receives the set of input code from the parallel-to-serial converter and receives the set of coefficient code, and then performs a passive or active correlation operation on the set of input code and the set of coefficient code to output a correlation value to the access point for synchronizing signals of the communication device and the access point.

摘要翻译： 一种用于通信设备和接入点的同步器，其安装在通信设备内部并且包括产生一组系数代码的系数发生器。 并行到串行转换器从接入点接收一组输入代码，对该组输入代码执行并行到串行转换并输出结果。 系数元素阵列包括彼此互连的多个系数元素。 每个系数元件从并行到串行转换器接收一组输入代码并接收该系数码集合，然后对该组输入码和该系数码组进行无源或主动相关运算以输出 与用于同步通信设备和接入点的信号的接入点的相关值。

公开(公告)号：US20100142506A1

公开(公告)日：2010-06-10

申请号：US12419911

申请日：2009-04-07

申请人： Yuan-Sun Chu ,  Ting-Huan Li ,  Yi-Ren Chen ,  Chia-Ying Huang ,  Kuo-Hua Pu ,  Chi-Fang Li

发明人： Yuan-Sun Chu ,  Ting-Huan Li ,  Yi-Ren Chen ,  Chia-Ying Huang ,  Kuo-Hua Pu ,  Chi-Fang Li

IPC分类号： H04J3/06 ,  H04B7/216

CPC分类号： H04W56/00 ,  H04B1/7075 ,  H04B2201/70707 ,  H04W92/10

摘要： The present invention discloses a synchronizer for a communication device and an access point, which is installed inside the communication device and comprises a coefficient generator generating a set of coefficient code; a parallel-to-serial converter receiving a set of input code from an access point, performing a parallel-to-serial conversion on the set of input code and outputting a result; and a coefficient element array including a plurality of coefficient elements interconnecting with each other, wherein each of the coefficient elements receives the set of input code from the parallel-to-serial converter and receives the set of coefficient code, and then performs a passive or active correlation operation on the set of input code and the set of coefficient code to output a correlation value to the access point for synchronizing signals of the communication device and the access point. The present invention has the synchronization functions of two communication systems—WCDMA and CDMA 2000, and thus can reduce the fabrication cost and increase convenience of communication.

摘要翻译： 本发明公开了一种用于通信设备和接入点的同步器，其安装在通信设备内部并且包括产生一组系数代码的系数发生器; 并行 - 串行转换器，从接入点接收一组输入代码，对所述一组输入代码执行并行到串行转换并输出结果; 以及包括彼此互连的多个系数元素的系数元素阵列，其中每个系数元件从并行到串行转换器接收一组输入代码并接收该组系数代码，然后执行被动或 对输入代码集合和系数码集合进行主动相关运算，以将相关值输出到用于同步通信设备和接入点的信号的接入点。 本发明具有WCDMA和CDMA2000两种通信系统的同步功能，从而可以降低制造成本并增加通信的便利性。