公开(公告)号：US20100173469A1

公开(公告)日：2010-07-08

申请号：US12651781

申请日：2010-01-04

申请人： Hak-Sun Lee ,  Kyoung-Sub Shin ,  Jeong-Dong Choe

发明人： Hak-Sun Lee ,  Kyoung-Sub Shin ,  Jeong-Dong Choe

IPC分类号： H01L21/76

CPC分类号： H01L27/11568

摘要： Some methods are directed to manufacturing charge trap-type non-volatile memory devices. An isolation layer pattern can be formed that extends in a first direction in a substrate. A recess unit is formed in the substrate by recessing an exposed surface of the substrate adjacent to the isolation layer pattern. A tunnel insulating layer and a charge trap layer are sequentially formed on the substrate. The tunnel insulating layer and the charge trap layer are patterned to form an isolated island-shaped tunnel insulating layer pattern and an isolated island-shaped charge trap layer pattern by etching defined regions of the substrate, the isolation layer pattern, the tunnel insulating layer, and the charge trap layer until a top surface of the charge trap layer that is disposed on a bottom surface of the recess unit is aligned with a top surface of the isolation layer pattern. A blocking insulating layer is formed that covers the charge trap layer pattern, the isolation layer pattern, and a defined region of the substrate interposed between the charge trap patterns. A gate electrode pattern is formed on the blocking insulating layer to face the charge trap layer pattern. This manufacturing process may reduce charge spreading between unit memory cells and/or may prevent/avoid reduction in the breakdown voltage of the blocking insulating layer.

摘要翻译： 一些方法涉及制造电荷陷阱型非易失性存储器件。 可以形成在衬底中沿第一方向延伸的隔离层图案。 通过使邻近隔离层图案的基板的暴露表面凹陷而在基板中形成凹部单元。 隧道绝缘层和电荷陷阱层依次形成在基板上。 图案化隧道绝缘层和电荷陷阱层，通过蚀刻衬底的限定区域，隔离层图案，隧道绝缘层，隔离层状图案，隔离层状图案，隧道绝缘层， 并且电荷陷阱层直到设置在凹陷单元的底表面上的电荷陷阱层的顶表面与隔离层图案的顶表面对准。 形成了覆盖电荷陷阱层图案，隔离层图案和插入在电荷阱图案之间的基板的限定区域的阻挡绝缘层。 在阻挡绝缘层上形成面对电荷陷阱层图案的栅电极图案。 该制造过程可以减小单元存储单元之间的电荷扩展和/或可以防止/避免阻塞绝缘层的击穿电压的降低。

公开(公告)号：US08178408B2

公开(公告)日：2012-05-15

申请号：US12651781

申请日：2010-01-04

申请人： Hak-Sun Lee ,  Kyoung-Sub Shin ,  Jeong-Dong Choe

发明人： Hak-Sun Lee ,  Kyoung-Sub Shin ,  Jeong-Dong Choe

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L27/11568

摘要： Some methods are directed to manufacturing charge trap-type non-volatile memory devices. An isolation layer pattern can be formed that extends in a first direction in a substrate. A recess unit is formed in the substrate by recessing an exposed surface of the substrate adjacent to the isolation layer pattern. A tunnel insulating layer and a charge trap layer are sequentially formed on the substrate. The tunnel insulating layer and the charge trap layer are patterned to form an isolated island-shaped tunnel insulating layer pattern and an isolated island-shaped charge trap layer pattern by etching defined regions of the substrate, the isolation layer pattern, the tunnel insulating layer, and the charge trap layer until a top surface of the charge trap layer that is disposed on a bottom surface of the recess unit is aligned with a top surface of the isolation layer pattern. A blocking insulating layer is formed that covers the charge trap layer pattern, the isolation layer pattern, and a defined region of the substrate interposed between the charge trap patterns. A gate electrode pattern is formed on the blocking insulating layer to face the charge trap layer pattern. This manufacturing process may reduce charge spreading between unit memory cells and/or may prevent/avoid reduction in the breakdown voltage of the blocking insulating layer.

摘要翻译： 一些方法涉及制造电荷陷阱型非易失性存储器件。 可以形成在衬底中沿第一方向延伸的隔离层图案。 通过使邻近隔离层图案的基板的暴露表面凹陷而在基板中形成凹部单元。 隧道绝缘层和电荷陷阱层依次形成在基板上。 图案化隧道绝缘层和电荷陷阱层，通过蚀刻衬底的限定区域，隔离层图案，隧道绝缘层，隔离层状图案，隔离层状图案，隧道绝缘层， 并且电荷陷阱层直到设置在凹陷单元的底表面上的电荷陷阱层的顶表面与隔离层图案的顶表面对准。 形成了覆盖电荷陷阱层图案，隔离层图案和插入在电荷阱图案之间的基板的限定区域的阻挡绝缘层。 在阻挡绝缘层上形成面对电荷陷阱层图案的栅电极图案。 该制造过程可以减小单元存储单元之间的电荷扩展和/或可以防止/避免阻塞绝缘层的击穿电压的降低。

公开(公告)号：US08003469B2

公开(公告)日：2011-08-23

申请号：US12611362

申请日：2009-11-03

申请人： Hak-Sun Lee ,  Kyoung-Sub Shin

发明人： Hak-Sun Lee ,  Kyoung-Sub Shin

IPC分类号： H01L21/336

CPC分类号： H01L27/11573

摘要： A non-volatile semiconductor device includes a memory cell in a first area of a substrate, a low voltage transistor in a second area of the substrate, and a high voltage transistor in a third area of the substrate. The memory cell includes a tunnel insulation layer formed on the substrate, a charge trapping layer pattern formed on the tunnel insulation layer in the first area of the substrate, a blocking layer pattern formed on the charge trapping layer pattern and a control gate formed on the blocking layer pattern. The control gate has a width substantially smaller than a width of the blocking layer pattern and the width of the control gate is substantially smaller than a width of the charge trapping layer pattern. In addition, an offset is formed between the control gate and the blocking layer pattern such that a spacer is not formed on a sidewall of the control gate.

摘要翻译： 非易失性半导体器件包括在衬底的第一区域中的存储单元，在衬底的第二区域中的低电压晶体管，以及在衬底的第三区域中的高压晶体管。 存储单元包括形成在基板上的隧道绝缘层，形成在基板的第一区域中的隧道绝缘层上的电荷俘获层图案，形成在电荷俘获层图案上的阻挡层图案和形成在基板上的控制栅极 阻挡层图案。 控制栅极的宽度显着小于阻挡层图案的宽度，并且控制栅极的宽度基本上小于电荷俘获层图案的宽度。 此外，在控制栅极和阻挡层图案之间形成偏移，使得在控制栅极的侧壁上未形成间隔物。

公开(公告)号：US08669622B2

公开(公告)日：2014-03-11

申请号：US13157753

申请日：2011-06-10

申请人： Hak-Sun Lee ,  Kyoung-Sub Shin

发明人： Hak-Sun Lee ,  Kyoung-Sub Shin

IPC分类号： H01L21/70

CPC分类号： H01L27/11573

摘要： A non-volatile semiconductor device includes a memory cell in a first area of a substrate, a low voltage transistor in a second area of the substrate, and a high voltage transistor in a third area of the substrate. The memory cell includes a tunnel insulation layer formed on the substrate, a charge trapping layer pattern formed on the tunnel insulation layer in the first area of the substrate, a blocking layer pattern formed on the charge trapping layer pattern and a control gate formed on the blocking layer pattern. The control gate has a width substantially smaller than a width of the blocking layer pattern and the width of the control gate is substantially smaller than a width of the charge trapping layer pattern. In addition, an offset is formed between the control gate and the blocking layer pattern such that a spacer is not formed on a sidewall of the control gate.

摘要翻译： 非易失性半导体器件包括在衬底的第一区域中的存储单元，在衬底的第二区域中的低电压晶体管，以及在衬底的第三区域中的高压晶体管。 存储单元包括形成在基板上的隧道绝缘层，形成在基板的第一区域中的隧道绝缘层上的电荷俘获层图案，形成在电荷俘获层图案上的阻挡层图案和形成在基板上的控制栅极 阻挡层图案。 控制栅极的宽度显着小于阻挡层图案的宽度，并且控制栅极的宽度基本上小于电荷俘获层图案的宽度。 此外，在控制栅极和阻挡层图案之间形成偏移，使得在控制栅极的侧壁上未形成间隔物。