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    METHODS OF MANUFACTURING CHARGE TRAP-TYPE NON-VOLATILE MEMORY DEVICES
    1.
    发明申请
    METHODS OF MANUFACTURING CHARGE TRAP-TYPE NON-VOLATILE MEMORY DEVICES 有权
    制造电荷陷波型非易失性存储器件的方法

    公开(公告)号：US20100173469A1

    公开(公告)日：2010-07-08

    申请号：US12651781

    申请日：2010-01-04

    申请人： Hak-Sun Lee ,  Kyoung-Sub Shin ,  Jeong-Dong Choe

    发明人： Hak-Sun Lee ,  Kyoung-Sub Shin ,  Jeong-Dong Choe

    IPC分类号： H01L21/76

    CPC分类号： H01L27/11568

    摘要： Some methods are directed to manufacturing charge trap-type non-volatile memory devices. An isolation layer pattern can be formed that extends in a first direction in a substrate. A recess unit is formed in the substrate by recessing an exposed surface of the substrate adjacent to the isolation layer pattern. A tunnel insulating layer and a charge trap layer are sequentially formed on the substrate. The tunnel insulating layer and the charge trap layer are patterned to form an isolated island-shaped tunnel insulating layer pattern and an isolated island-shaped charge trap layer pattern by etching defined regions of the substrate, the isolation layer pattern, the tunnel insulating layer, and the charge trap layer until a top surface of the charge trap layer that is disposed on a bottom surface of the recess unit is aligned with a top surface of the isolation layer pattern. A blocking insulating layer is formed that covers the charge trap layer pattern, the isolation layer pattern, and a defined region of the substrate interposed between the charge trap patterns. A gate electrode pattern is formed on the blocking insulating layer to face the charge trap layer pattern. This manufacturing process may reduce charge spreading between unit memory cells and/or may prevent/avoid reduction in the breakdown voltage of the blocking insulating layer.

    摘要翻译： 一些方法涉及制造电荷陷阱型非易失性存储器件。 可以形成在衬底中沿第一方向延伸的隔离层图案。 通过使邻近隔离层图案的基板的暴露表面凹陷而在基板中形成凹部单元。 隧道绝缘层和电荷陷阱层依次形成在基板上。 图案化隧道绝缘层和电荷陷阱层，通过蚀刻衬底的限定区域，隔离层图案，隧道绝缘层，隔离层状图案，隔离层状图案，隧道绝缘层， 并且电荷陷阱层直到设置在凹陷单元的底表面上的电荷陷阱层的顶表面与隔离层图案的顶表面对准。 形成了覆盖电荷陷阱层图案，隔离层图案和插入在电荷阱图案之间的基板的限定区域的阻挡绝缘层。 在阻挡绝缘层上形成面对电荷陷阱层图案的栅电极图案。 该制造过程可以减小单元存储单元之间的电荷扩展和/或可以防止/避免阻塞绝缘层的击穿电压的降低。

    Methods of manufacturing charge trap-type non-volatile memory devices
    2.
    发明授权
    Methods of manufacturing charge trap-type non-volatile memory devices 有权
    制造电荷陷阱型非易失性存储器件的方法

    公开(公告)号：US08178408B2

    公开(公告)日：2012-05-15

    申请号：US12651781

    申请日：2010-01-04

    申请人： Hak-Sun Lee ,  Kyoung-Sub Shin ,  Jeong-Dong Choe

    发明人： Hak-Sun Lee ,  Kyoung-Sub Shin ,  Jeong-Dong Choe

    IPC分类号： H01L21/336 ,  H01L21/3205

    CPC分类号： H01L27/11568

    摘要： Some methods are directed to manufacturing charge trap-type non-volatile memory devices. An isolation layer pattern can be formed that extends in a first direction in a substrate. A recess unit is formed in the substrate by recessing an exposed surface of the substrate adjacent to the isolation layer pattern. A tunnel insulating layer and a charge trap layer are sequentially formed on the substrate. The tunnel insulating layer and the charge trap layer are patterned to form an isolated island-shaped tunnel insulating layer pattern and an isolated island-shaped charge trap layer pattern by etching defined regions of the substrate, the isolation layer pattern, the tunnel insulating layer, and the charge trap layer until a top surface of the charge trap layer that is disposed on a bottom surface of the recess unit is aligned with a top surface of the isolation layer pattern. A blocking insulating layer is formed that covers the charge trap layer pattern, the isolation layer pattern, and a defined region of the substrate interposed between the charge trap patterns. A gate electrode pattern is formed on the blocking insulating layer to face the charge trap layer pattern. This manufacturing process may reduce charge spreading between unit memory cells and/or may prevent/avoid reduction in the breakdown voltage of the blocking insulating layer.

    摘要翻译： 一些方法涉及制造电荷陷阱型非易失性存储器件。 可以形成在衬底中沿第一方向延伸的隔离层图案。 通过使邻近隔离层图案的基板的暴露表面凹陷而在基板中形成凹部单元。 隧道绝缘层和电荷陷阱层依次形成在基板上。 图案化隧道绝缘层和电荷陷阱层，通过蚀刻衬底的限定区域，隔离层图案，隧道绝缘层，隔离层状图案，隔离层状图案，隧道绝缘层， 并且电荷陷阱层直到设置在凹陷单元的底表面上的电荷陷阱层的顶表面与隔离层图案的顶表面对准。 形成了覆盖电荷陷阱层图案，隔离层图案和插入在电荷阱图案之间的基板的限定区域的阻挡绝缘层。 在阻挡绝缘层上形成面对电荷陷阱层图案的栅电极图案。 该制造过程可以减小单元存储单元之间的电荷扩展和/或可以防止/避免阻塞绝缘层的击穿电压的降低。

    Synchronous pulse plasma etching equipment and method of fabricating a semiconductor device
    4.
    发明授权
    Synchronous pulse plasma etching equipment and method of fabricating a semiconductor device 有权
    同步脉冲等离子体蚀刻设备及制造半导体器件的方法

    公开(公告)号：US08460508B2

    公开(公告)日：2013-06-11

    申请号：US12591602

    申请日：2009-11-24

    申请人： Ken Tokashiki ,  Hong Cho ,  Jeong-Dong Choe

    发明人： Ken Tokashiki ,  Hong Cho ,  Jeong-Dong Choe

    IPC分类号： H01L21/3065 ,  H01L21/302 ,  C23C16/00 ,  C23C16/50 ,  C23C16/52

    CPC分类号： H01J37/32165 ,  H01J37/32082 ,  H01J37/32174

    摘要： Synchronous pulse plasma etching equipment includes a first electrode and one or more second electrodes configured to generate plasma in a plasma etching chamber. A first radio frequency power output unit is configured to apply a first radio frequency power having a first frequency and a first duty ratio to the first electrode, and to output a control signal including information about a phase of the first radio frequency power. At least one second radio frequency power output unit is configured to apply a second radio frequency power having a second frequency and a second duty ratio to a corresponding second electrode among the second electrodes. The second radio frequency power output unit is configured to control the second radio frequency power to be synchronized with the first radio frequency power or to have a phase difference from the first radio frequency power in response to the control signal.

    摘要翻译： 同步脉冲等离子体蚀刻设备包括第一电极和被配置为在等离子体蚀刻室中产生等离子体的一个或多个第二电极。 第一射频功率输出单元被配置为向第一电极施加具有第一频率和第一占空比的第一射频功率，并且输出包括关于第一射频功率的相位的信息的控制信号。 至少一个第二射频功率输出单元被配置为将具有第二频率和第二占空比的第二射频功率应用于第二电极中的对应的第二电极。 第二射频功率输出单元被配置为响应于控制信号控制与第一射频功率同步的第二射频功率或者与第一射频功率相位差。

    Metal Oxide Semiconductor Field Effect Transistors (MOSFETS) Including Recessed Channel Regions
    6.
    发明申请
    Metal Oxide Semiconductor Field Effect Transistors (MOSFETS) Including Recessed Channel Regions 审中-公开
    金属氧化物半导体场效应晶体管（MOSFET）包括嵌入式通道区域

    公开(公告)号：US20110079831A1

    公开(公告)日：2011-04-07

    申请号：US12966362

    申请日：2010-12-13

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Chang-Sub Lee ,  Jeong-Dong Choe

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Chang-Sub Lee ,  Jeong-Dong Choe

    IPC分类号： H01L29/772

    CPC分类号： H01L29/66583 ,  H01L29/1037 ,  H01L29/66651

    摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided having an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is between the source region and the drain region. A channel region is provided between the source and drain regions. The channel region has a recessed region that is lower than bottom surfaces of the source and drain regions. Related methods of fabricating transistors are also provided.

    摘要翻译： 金属氧化物半导体（MOS）晶体管的单位电池在集成电路基板上具有集成电路基板和MOS晶体管。 MOS晶体管包括源极区，漏极区和栅极。 栅极在源极区域和漏极区域之间。 在源区和漏区之间提供沟道区。 沟道区具有比源区和漏区的底表面低的凹陷区域。 还提供了制造晶体管的相关方法。

    Multichannel Metal Oxide Semiconductor (MOS) Transistors
    7.
    发明申请
    Multichannel Metal Oxide Semiconductor (MOS) Transistors 审中-公开
    多通道金属氧化物半导体（MOS）晶体管

    公开(公告)号：US20100109087A1

    公开(公告)日：2010-05-06

    申请号：US12687613

    申请日：2010-01-14

    申请人： Kyoung-Hwan Yeo ,  Dong-Gun Park ,  Jeong-Dong Choe

    发明人： Kyoung-Hwan Yeo ,  Dong-Gun Park ,  Jeong-Dong Choe

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66484 ,  H01L21/8221 ,  H01L21/823412 ,  H01L27/0688 ,  H01L29/7831

    摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate an a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is positioned between the source region and the drain region. A horizontal channel is provided between the source and drain regions. The horizontal channel includes at least two spaced apart horizontal channel regions. Related methods of fabricating MOS transistors are also provided.

    摘要翻译： 提供金属氧化物半导体（MOS）晶体管的单元电池，其包括集成电路基板和集成电路基板上的MOS晶体管。 MOS晶体管包括源极区，漏极区和栅极。 栅极位于源极区域和漏极区域之间。 在源区和漏区之间提供水平通道。 水平通道包括至少两个间隔开的水平通道区域。 还提供了制造MOS晶体管的相关方法。

    Vertical Channel Fin Field-Effect Transistors Having Increased Source/Drain Contact Area and Methods for Fabricating the Same
    8.
    发明申请
    Vertical Channel Fin Field-Effect Transistors Having Increased Source/Drain Contact Area and Methods for Fabricating the Same 有权
    具有增加的源极/漏极接触面积的垂直沟道鳍效应晶体管及其制造方法

    公开(公告)号：US20100044784A1

    公开(公告)日：2010-02-25

    申请号：US12613025

    申请日：2009-11-05

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Dong-Won Kim

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Dong-Won Kim

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/78618

    摘要： A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts are formed on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode. The channel region may be narrower than the first and second source/drain regions of the fin-shaped active region.

    摘要翻译： 翅片场效应晶体管（FinFET）器件包括其中具有第一和第二源极/漏极区域的鳍状有源区域以及从半导体衬底垂直突出的沟道区域。 栅电极形成在沟道区的上表面和侧壁上。 第一和第二源极/漏极触点形成在栅极电极的相对侧的鳍状有源区域的第一和第二源极/漏极区域的相应上表面和侧壁上。 沟道区域可以比鳍状有源区域的第一和第二源极/漏极区域窄。