公开(公告)号：US20100173469A1

公开(公告)日：2010-07-08

申请号：US12651781

申请日：2010-01-04

申请人： Hak-Sun Lee ,  Kyoung-Sub Shin ,  Jeong-Dong Choe

发明人： Hak-Sun Lee ,  Kyoung-Sub Shin ,  Jeong-Dong Choe

IPC分类号： H01L21/76

CPC分类号： H01L27/11568

摘要： Some methods are directed to manufacturing charge trap-type non-volatile memory devices. An isolation layer pattern can be formed that extends in a first direction in a substrate. A recess unit is formed in the substrate by recessing an exposed surface of the substrate adjacent to the isolation layer pattern. A tunnel insulating layer and a charge trap layer are sequentially formed on the substrate. The tunnel insulating layer and the charge trap layer are patterned to form an isolated island-shaped tunnel insulating layer pattern and an isolated island-shaped charge trap layer pattern by etching defined regions of the substrate, the isolation layer pattern, the tunnel insulating layer, and the charge trap layer until a top surface of the charge trap layer that is disposed on a bottom surface of the recess unit is aligned with a top surface of the isolation layer pattern. A blocking insulating layer is formed that covers the charge trap layer pattern, the isolation layer pattern, and a defined region of the substrate interposed between the charge trap patterns. A gate electrode pattern is formed on the blocking insulating layer to face the charge trap layer pattern. This manufacturing process may reduce charge spreading between unit memory cells and/or may prevent/avoid reduction in the breakdown voltage of the blocking insulating layer.

摘要翻译： 一些方法涉及制造电荷陷阱型非易失性存储器件。 可以形成在衬底中沿第一方向延伸的隔离层图案。 通过使邻近隔离层图案的基板的暴露表面凹陷而在基板中形成凹部单元。 隧道绝缘层和电荷陷阱层依次形成在基板上。 图案化隧道绝缘层和电荷陷阱层，通过蚀刻衬底的限定区域，隔离层图案，隧道绝缘层，隔离层状图案，隔离层状图案，隧道绝缘层， 并且电荷陷阱层直到设置在凹陷单元的底表面上的电荷陷阱层的顶表面与隔离层图案的顶表面对准。 形成了覆盖电荷陷阱层图案，隔离层图案和插入在电荷阱图案之间的基板的限定区域的阻挡绝缘层。 在阻挡绝缘层上形成面对电荷陷阱层图案的栅电极图案。 该制造过程可以减小单元存储单元之间的电荷扩展和/或可以防止/避免阻塞绝缘层的击穿电压的降低。

公开(公告)号：US08178408B2

公开(公告)日：2012-05-15

申请号：US12651781

申请日：2010-01-04

申请人： Hak-Sun Lee ,  Kyoung-Sub Shin ,  Jeong-Dong Choe

发明人： Hak-Sun Lee ,  Kyoung-Sub Shin ,  Jeong-Dong Choe

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L27/11568

摘要： Some methods are directed to manufacturing charge trap-type non-volatile memory devices. An isolation layer pattern can be formed that extends in a first direction in a substrate. A recess unit is formed in the substrate by recessing an exposed surface of the substrate adjacent to the isolation layer pattern. A tunnel insulating layer and a charge trap layer are sequentially formed on the substrate. The tunnel insulating layer and the charge trap layer are patterned to form an isolated island-shaped tunnel insulating layer pattern and an isolated island-shaped charge trap layer pattern by etching defined regions of the substrate, the isolation layer pattern, the tunnel insulating layer, and the charge trap layer until a top surface of the charge trap layer that is disposed on a bottom surface of the recess unit is aligned with a top surface of the isolation layer pattern. A blocking insulating layer is formed that covers the charge trap layer pattern, the isolation layer pattern, and a defined region of the substrate interposed between the charge trap patterns. A gate electrode pattern is formed on the blocking insulating layer to face the charge trap layer pattern. This manufacturing process may reduce charge spreading between unit memory cells and/or may prevent/avoid reduction in the breakdown voltage of the blocking insulating layer.

摘要翻译： 一些方法涉及制造电荷陷阱型非易失性存储器件。 可以形成在衬底中沿第一方向延伸的隔离层图案。 通过使邻近隔离层图案的基板的暴露表面凹陷而在基板中形成凹部单元。 隧道绝缘层和电荷陷阱层依次形成在基板上。 图案化隧道绝缘层和电荷陷阱层，通过蚀刻衬底的限定区域，隔离层图案，隧道绝缘层，隔离层状图案，隔离层状图案，隧道绝缘层， 并且电荷陷阱层直到设置在凹陷单元的底表面上的电荷陷阱层的顶表面与隔离层图案的顶表面对准。 形成了覆盖电荷陷阱层图案，隔离层图案和插入在电荷阱图案之间的基板的限定区域的阻挡绝缘层。 在阻挡绝缘层上形成面对电荷陷阱层图案的栅电极图案。 该制造过程可以减小单元存储单元之间的电荷扩展和/或可以防止/避免阻塞绝缘层的击穿电压的降低。

公开(公告)号：US20100237401A1

公开(公告)日：2010-09-23

申请号：US12726836

申请日：2010-03-18

申请人： JEONG-DONG CHOE ,  Kyoung-Sub Shin ,  Kyoung-Hwan Yeo

发明人： JEONG-DONG CHOE ,  Kyoung-Sub Shin ,  Kyoung-Hwan Yeo

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/513

摘要： Gate structures of semiconductor devices and methods of forming gate structures of semiconductor devices are provided. A first insulating pattern may be disposed on an active region of a semiconductor substrate. A data storage pattern may be disposed on the first insulating pattern. A second insulating pattern may be disposed on the data storage pattern and may contact the data storage pattern. A first conductive pattern may conform to the second insulating pattern and to sidewalls of a mold comprising the second insulating pattern. A second conductive pattern may be disposed within a cavity defined by the first conductive pattern. Spacers may be formed on sidewalls of at least one of the first insulating pattern, the data storage pattern, the second insulating pattern, and the conductive pattern.

摘要翻译： 提供了半导体器件的栅极结构和形成半导体器件的栅极结构的方法。 第一绝缘图案可以设置在半导体衬底的有源区上。 数据存储图案可以设置在第一绝缘图案上。 第二绝缘图案可以设置在数据存储图案上并且可以接触数据存储图案。 第一导电图案可以符合第二绝缘图案以及包括第二绝缘图案的模具的侧壁。 第二导电图案可以设置在由第一导电图案限定的空腔内。 间隔件可以形成在第一绝缘图案，数据存储图案，第二绝缘图案和导电图案中的至少一个的侧壁上。

公开(公告)号：US08669622B2

公开(公告)日：2014-03-11

申请号：US13157753

申请日：2011-06-10

申请人： Hak-Sun Lee ,  Kyoung-Sub Shin

发明人： Hak-Sun Lee ,  Kyoung-Sub Shin

IPC分类号： H01L21/70

CPC分类号： H01L27/11573

摘要： A non-volatile semiconductor device includes a memory cell in a first area of a substrate, a low voltage transistor in a second area of the substrate, and a high voltage transistor in a third area of the substrate. The memory cell includes a tunnel insulation layer formed on the substrate, a charge trapping layer pattern formed on the tunnel insulation layer in the first area of the substrate, a blocking layer pattern formed on the charge trapping layer pattern and a control gate formed on the blocking layer pattern. The control gate has a width substantially smaller than a width of the blocking layer pattern and the width of the control gate is substantially smaller than a width of the charge trapping layer pattern. In addition, an offset is formed between the control gate and the blocking layer pattern such that a spacer is not formed on a sidewall of the control gate.

摘要翻译： 非易失性半导体器件包括在衬底的第一区域中的存储单元，在衬底的第二区域中的低电压晶体管，以及在衬底的第三区域中的高压晶体管。 存储单元包括形成在基板上的隧道绝缘层，形成在基板的第一区域中的隧道绝缘层上的电荷俘获层图案，形成在电荷俘获层图案上的阻挡层图案和形成在基板上的控制栅极 阻挡层图案。 控制栅极的宽度显着小于阻挡层图案的宽度，并且控制栅极的宽度基本上小于电荷俘获层图案的宽度。 此外，在控制栅极和阻挡层图案之间形成偏移，使得在控制栅极的侧壁上未形成间隔物。

公开(公告)号：US20110233653A1

公开(公告)日：2011-09-29

申请号：US13157753

申请日：2011-06-10

申请人： Hak-Sun LEE ,  Kyoung-Sub Shin

发明人： Hak-Sun LEE ,  Kyoung-Sub Shin

IPC分类号： H01L29/792

CPC分类号： H01L27/11573

摘要： A non-volatile semiconductor device includes a memory cell in a first area of a substrate, a low voltage transistor in a second area of the substrate, and a high voltage transistor in a third area of the substrate. The memory cell includes a tunnel insulation layer formed on the substrate, a charge trapping layer pattern formed on the tunnel insulation layer in the first area of the substrate, a blocking layer pattern formed on the charge trapping layer pattern and a control gate formed on the blocking layer pattern. The control gate has a width substantially smaller than a width of the blocking layer pattern and the width of the control gate is substantially smaller than a width of the charge trapping layer pattern. In addition, an offset is formed between the control gate and the blocking layer pattern such that a spacer is not formed on a sidewall of the control gate.

摘要翻译： 非易失性半导体器件包括在衬底的第一区域中的存储单元，在衬底的第二区域中的低电压晶体管，以及在衬底的第三区域中的高压晶体管。 存储单元包括形成在基板上的隧道绝缘层，形成在基板的第一区域中的隧道绝缘层上的电荷俘获层图案，形成在电荷俘获层图案上的阻挡层图案和形成在基板上的控制栅极 阻挡层图案。 控制栅极的宽度显着小于阻挡层图案的宽度，并且控制栅极的宽度基本上小于电荷俘获层图案的宽度。 此外，在控制栅极和阻挡层图案之间形成偏移，使得在控制栅极的侧壁上未形成间隔物。

公开(公告)号：US08003469B2

公开(公告)日：2011-08-23

申请号：US12611362

申请日：2009-11-03

申请人： Hak-Sun Lee ,  Kyoung-Sub Shin

发明人： Hak-Sun Lee ,  Kyoung-Sub Shin

IPC分类号： H01L21/336

CPC分类号： H01L27/11573

摘要： A non-volatile semiconductor device includes a memory cell in a first area of a substrate, a low voltage transistor in a second area of the substrate, and a high voltage transistor in a third area of the substrate. The memory cell includes a tunnel insulation layer formed on the substrate, a charge trapping layer pattern formed on the tunnel insulation layer in the first area of the substrate, a blocking layer pattern formed on the charge trapping layer pattern and a control gate formed on the blocking layer pattern. The control gate has a width substantially smaller than a width of the blocking layer pattern and the width of the control gate is substantially smaller than a width of the charge trapping layer pattern. In addition, an offset is formed between the control gate and the blocking layer pattern such that a spacer is not formed on a sidewall of the control gate.

摘要翻译： 非易失性半导体器件包括在衬底的第一区域中的存储单元，在衬底的第二区域中的低电压晶体管，以及在衬底的第三区域中的高压晶体管。 存储单元包括形成在基板上的隧道绝缘层，形成在基板的第一区域中的隧道绝缘层上的电荷俘获层图案，形成在电荷俘获层图案上的阻挡层图案和形成在基板上的控制栅极 阻挡层图案。 控制栅极的宽度显着小于阻挡层图案的宽度，并且控制栅极的宽度基本上小于电荷俘获层图案的宽度。 此外，在控制栅极和阻挡层图案之间形成偏移，使得在控制栅极的侧壁上未形成间隔物。

公开(公告)号：US20100112768A1

公开(公告)日：2010-05-06

申请号：US12611362

申请日：2009-11-03

申请人： Hak-Sun LEE ,  Kyoung-Sub Shin

发明人： Hak-Sun LEE ,  Kyoung-Sub Shin

IPC分类号： H01L21/336

CPC分类号： H01L27/11573

摘要： A non-volatile semiconductor device includes a memory cell in a first area of a substrate, a low voltage transistor in a second area of the substrate, and a high voltage transistor in a third area of the substrate. The memory cell includes a tunnel insulation layer formed on the substrate, a charge trapping layer pattern formed on the tunnel insulation layer in the first area of the substrate, a blocking layer pattern formed on the charge trapping layer pattern and a control gate formed on the blocking layer pattern. The control gate has a width substantially smaller than a width of the blocking layer pattern and the width of the control gate is substantially smaller than a width of the charge trapping layer pattern. In addition, an offset is formed between the control gate and the blocking layer pattern such that a spacer is not formed on a sidewall of the control gate.

摘要翻译： 非易失性半导体器件包括在衬底的第一区域中的存储单元，在衬底的第二区域中的低电压晶体管，以及在衬底的第三区域中的高压晶体管。 存储单元包括形成在基板上的隧道绝缘层，形成在基板的第一区域中的隧道绝缘层上的电荷俘获层图案，形成在电荷俘获层图案上的阻挡层图案和形成在基板上的控制栅极 阻挡层图案。 控制栅极的宽度显着小于阻挡层图案的宽度，并且控制栅极的宽度基本上小于电荷俘获层图案的宽度。 此外，在控制栅极和阻挡层图案之间形成偏移，使得在控制栅极的侧壁上未形成间隔物。

公开(公告)号：US09899404B2

公开(公告)日：2018-02-20

申请号：US14957099

申请日：2015-12-02

申请人： Jin-Hyuk Yoo ,  Dae-Hyun Jang ,  Yoo-Chul Kong ,  Kyoung-Sub Shin

发明人： Jin-Hyuk Yoo ,  Dae-Hyun Jang ,  Yoo-Chul Kong ,  Kyoung-Sub Shin

IPC分类号： H01L29/76 ,  H01L27/1157 ,  H01L23/48 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/06

CPC分类号： H01L27/1157 ,  H01L23/48 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.

公开(公告)号：US20110284163A1

公开(公告)日：2011-11-24

申请号：US13086475

申请日：2011-04-14

申请人： Jun-Ho Yoon ,  Kyoung-Sub Shin ,  Woo-Seok Kim ,  Dong-Kwon Kim ,  Hyung-Yong Kim ,  Yong-Ho Jeon

发明人： Jun-Ho Yoon ,  Kyoung-Sub Shin ,  Woo-Seok Kim ,  Dong-Kwon Kim ,  Hyung-Yong Kim ,  Yong-Ho Jeon

IPC分类号： H01L21/00 ,  C23F1/08

CPC分类号： H01L21/67069 ,  H01J37/32935 ,  H01J37/32972

摘要： A plasma processing apparatus includes a chamber for processing a substrate. A plasma generator is provided to generate plasma within the chamber. A window is provided in a sidewall of the chamber, and the window transmits light from the plasma within the chamber. A photocatalytic layer is provided on an inner surface of the window such that the photocatalytic layer is activated as a result of exposure to light from the plasma to decompose a residual product on the inner surface of the window.

摘要翻译： 等离子体处理装置包括用于处理基板的室。 提供等离子体发生器以在腔室内产生等离子体。 窗口设置在室的侧壁中，并且窗口从腔室内的等离子体透射光。 在窗的内表面上提供光催化层，使得光催化层由于暴露于等离子体的光而被激活，从而在窗的内表面上分解残留产物。

公开(公告)号：US08883588B2

公开(公告)日：2014-11-11

申请号：US13599233

申请日：2012-08-30

申请人： Sung-Soo Ahn ,  O Ik Kwon ,  Bum-Soo Kim ,  Hyun-Sung Kim ,  Kyoung-Sub Shin ,  Min-Kyung Yun ,  Seung-Pil Chung ,  Won-Bong Jung

发明人： Sung-Soo Ahn ,  O Ik Kwon ,  Bum-Soo Kim ,  Hyun-Sung Kim ,  Kyoung-Sub Shin ,  Min-Kyung Yun ,  Seung-Pil Chung ,  Won-Bong Jung

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L29/7883 ,  H01L21/7682 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42364 ,  H01L29/66825 ,  H01L29/7881

摘要： A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.

摘要翻译： 一种制造半导体器件的方法，所述方法包括在衬底的上表面上形成隧道绝缘层，在隧道绝缘层的上表面上形成栅极图案，在栅极图案的侧壁上形成覆盖层图案，并且在 隧道绝缘层的上表面，蚀刻未被栅极图案或覆盖层图案覆盖的隧道绝缘层的一部分以形成隧道绝缘层图案，并且在衬底的上表面上形成第一绝缘层 以覆盖栅极图案，覆盖层图案和隧道绝缘层图案，其中第一绝缘层在封盖层图案之间具有气隙。