公开(公告)号：US20110305100A1

公开(公告)日：2011-12-15

申请号：US13152316

申请日：2011-06-03

申请人： Hak-soo YU ,  In-gyu BAEK ,  Hong-sun Hwang ,  Young-kug MOON

发明人： Hak-soo YU ,  In-gyu BAEK ,  Hong-sun Hwang ,  Young-kug MOON

IPC分类号： G11C5/14

CPC分类号： G11C5/063 ,  G11C5/025

摘要： A semiconductor memory device including a plurality of layers each including a memory cell array and which are stacked over each other; and at least one power plane for supplying power to the layers. The power plane includes a region to which a power voltage is applied and a region to which a ground voltage is applied. The region to which a power voltage is applied is located adjacent to the region to which a ground voltage is applied, and forms a decoupling capacitor therebetween to decouple an influx of power noise to the layers or generation of power noise in the layers

摘要翻译： 一种半导体存储器件，包括多个层，每个层包括存储单元阵列并彼此堆叠; 以及用于向层供电的至少一个电力平面。 电力平面包括施加电源电压的区域和施加接地电压的区域。 施加电源电压的区域位于与施加接地电压的区域相邻的位置处，并且在其间形成去耦电容器以将功率噪声流入到层中或在层中产生功率噪声

公开(公告)号：US20120063194A1

公开(公告)日：2012-03-15

申请号：US13224410

申请日：2011-09-02

申请人： In-gyu BAEK ,  Hong-sun HWANG ,  Hak-soo YU ,  Chul-woo PARK

发明人： In-gyu BAEK ,  Hong-sun HWANG ,  Hak-soo YU ,  Chul-woo PARK

IPC分类号： G11C11/00 ,  H01L45/00

CPC分类号： H01L45/147 ,  G11C5/025 ,  G11C13/0002 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/14

摘要： Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.

摘要翻译： 具有包括基于电阻器开关的逻辑电路的堆叠结构的半导体存储器件。 半导体存储器件包括第一导线，其包括第一线部分和第二线部分，其中第一线部分和第二线部分通过布置在第一线部分和第二线部分之间的中间区域彼此电分离， 连接到第一线部分并存储数据的第一可变电阻材料膜和控制第一线部分和第二线部分之间的电连接的第二可变电阻材料膜。

公开(公告)号：US20140091274A1

公开(公告)日：2014-04-03

申请号：US13941835

申请日：2013-07-15

申请人： Young-bae KIM ,  Kyung-min KIM ,  In-gyu BAEK ,  Seong-jun PARK

发明人： Young-bae KIM ,  Kyung-min KIM ,  In-gyu BAEK ,  Seong-jun PARK

IPC分类号： H01L45/00

CPC分类号： H01L45/145 ,  B82Y40/00 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1675 ,  Y10S977/734 ,  Y10S977/842 ,  Y10S977/943

摘要： In one embodiment, a memory device includes a first electrode layer on a substrate; a data storing layer on the first electrode layer; and a second electrode layer on the data storing layer. At least one of the first and second electrode layers may be formed of a material having a conduction band offset that varies with an applied voltage. One of the first and second electrode layers may be connected to a bit line and the other may be connected to a word line. The first electrode layer may include one of graphene and metastable oxide. The second electrode layer may include one of graphene and metastable oxide.

摘要翻译： 在一个实施例中，存储器件包括在衬底上的第一电极层; 在第一电极层上的数据存储层; 和数据存储层上的第二电极层。 第一和第二电极层中的至少一个可以由具有随施加电压而变化的导带偏移的材料形成。 第一和第二电极层中的一个可以连接到位线，而另一个可以连接到字线。 第一电极层可以包括石墨烯和亚稳态氧化物之一。 第二电极层可以包括石墨烯和亚稳态氧化物之一。