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公开(公告)号：US5353424A
公开(公告)日：1994-10-04
申请号：US794865
申请日：1991-11-19
申请人： Hamid Partovi , William R. Wheeler , Michael Leary , Michael A. Case , Steven Butler , Rajesh Khanna
发明人： Hamid Partovi , William R. Wheeler , Michael Leary , Michael A. Case , Steven Butler , Rajesh Khanna
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F12/0864
摘要： A tag comparator and bank selector for a set-associative cache in a computer system operates in a minimum time so that a cache hit or miss signal is generated early in a memory cycle. The data memory of the cache has two (or more) banks, with a tag store for each bank, and the two banks are accessed separately and in parallel using the index (low order address bits) while the tag translation is in progress. Two bit-by-bit tag compares are performed, one for each tag store, producing two multibit match indications, one bit for each tag bit in each tag store. These two match indications are applied to two separate dynamic NOR gates, and the two outputs applied to a logic circuit to detect a hit and generate a bank-select output. There are four possible outcomes from the compare operation: both banks miss, left bank hits, right bank hits, and both banks hit. The later condition indicates a possible ambiguity, and neither data item should be used, so a miss is signalled. The comparator is in large part self-timed using a flow-through design, as distinguished from being enabled on clock edges. Delay elements in the bank select logic allow the banks to be timed against each other, and current limiters are employed to equalize the timing of miss signals, regardless of the number of match lines switching high (which is data dependent). An address producing 19-of-20 match bits will result in a NOR gate output of about the same timing as an address producing no match bits, even though the former will turn on only one transistor to discharge the precharged output node of the NOR gate, whereas the later will turn on twenty paths for discharge. Although a two-way set associative cache is shown herein as an example embodiment, one of the features of the invention is that higher levels of associativity, e.g., four-way and eight-way, are equally well accommodated.
摘要翻译： 用于计算机系统中的组相关高速缓存的标签比较器和存储体选择器在最小时间内操作，使得在存储器周期中早期产生高速缓存命中或未命中信号。 高速缓存的数据存储器具有两个（或更多个）存储体，每个存储体具有标签存储，并且当标签转换正在进行时，使用索引（低位地址位）分开存取和并行访问两个存储体。 执行两个逐位标签比较，每个标签存储一个，产生两个多位匹配指示，每个标签存储中每个标签位一位。 这两个匹配指示被应用于两个单独的动态NOR门，并且两个输出被施加到逻辑电路以检测命中并产生一个存储体选择输出。 比较操作有四个可能的结果：两家银行错失，左岸点击，右岸点击，两家银行都受到打击。 后面的条件表示可能的模糊性，并且都不应该使用数据项，所以发出了错误信号。 使用流通设计，比较器在很大程度上是自定时的，与时钟边沿不同。 银行选择逻辑中的延迟元素允许银行彼此定时，并且采用电流限制器来均衡缺失信号的定时，而不管匹配线的数量如何切换高（这取决于数据）。 产生20位20位匹配位的地址将导致与不产生不匹配位的地址大致相同的定时的或非门输出，即使前者将仅接通一个晶体管来放电NOR门的预充电输出节点 ，而后来将打开二十条出路。 尽管本文中示出了双向组关联高速缓存作为示例实施例，但是本发明的特征之一是更高级别的关联性，例如四路和八路同样适应。
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公开(公告)号：US5253203A
公开(公告)日：1993-10-12
申请号：US2689
申请日：1993-01-11
申请人： Hamid Partovi , Michael A. Case
发明人： Hamid Partovi , Michael A. Case
CPC分类号： G11C7/10 , G06F12/0893 , G06F12/1054
摘要： The physical organization of a memory cell array in an integrated circuit cache memory system is different from its logical organization because the bit lines of the array are divided into segments to physically divide the memory cell array into sub-arrays, and multiplexing the bit line segments of groups of neighboring bit lines are multiplexed to respective data lines. "Early" address bits control row decoders which select a row of memory cells in each sub-array to assert data signals on the bit line segments in each sub-array. "Late" address bits control the multiplexing of the data signals on the bit line segments to the data lines. By segmenting the bit lines, the number of "late" address bits is increased relative to the number of "early" address bits to increase the memory access speed in data processing systems that employ virtual addressing but store data in cache memory in association with physical addresses. The "late" address bits, for example, are a translated portion of a virtual address translated by a translation buffer, and the "early" address bits are an untranslated portion of the virtual address. Routing problems are avoided by extending the data lines in parallel with the bit lines over regions of the integrated circuit substrate allocated to the memory cells in the array, and forming the data lines in a metalization layer separate from and over a metalization layer of the bit lines. Each data line is multiplexed to multiple bit line segments to eliminate a final multiplexer to input/output lines.
摘要翻译： 集成电路高速缓冲存储器系统中的存储单元阵列的物理组织与其逻辑组织不同，因为阵列的位线被划分成段以物理地将存储单元阵列划分为子阵列，并且复用位线段 的相邻位线组被复用到相应的数据线。 “早期”地址位控制行解码器，其选择每个子阵列中的一行存储器单元以在每个子阵列中的位线段上断言数据信号。 “晚”地址位控制位线段上的数据信号到数据线的复用。 通过对位线进行分段，相对于“早期”地址位的数量“晚”地址位的数量增加，以增加采用虚拟寻址的数据处理系统中的存储器访问速度，而将数据与物理存储器相关联地存储在高速缓冲存储器中 地址 例如，“晚”地址位是由翻译缓冲器转换的虚拟地址的翻译部分，并且“早期”地址位是虚拟地址的未翻译部分。 通过在分配给阵列中的存储器单元的集成电路衬底的区域上与位线并行地延伸数据线来避免路由问题，并且在与位的金属化层分开的金属化层中形成数据线 线条。 每个数据线被复用到多个位线段以消除最后的多路复用器到输入/输出线。
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公开(公告)号：US5452085A
公开(公告)日：1995-09-19
申请号：US970378
申请日：1993-01-27
申请人： Robert D. Fancy , Michael A. Case
发明人： Robert D. Fancy , Michael A. Case
CPC分类号： G01J3/02 , G01J3/0208 , G01J3/021 , G01J3/0291
摘要： An optical input system for correcting astigmatism introduced by off-axis reflectors in a spectrograph includes an aspheric mirror producing a correcting factor which compensates for the spectrograph distortions and enables the spectrograph to produce multiple astigmatic light images at its two-dimensional charge-coupled-device output.
摘要翻译： 在光谱仪中用于校正由离轴反射器引入的像散的光学输入系统包括非球面镜，其产生补偿光谱失真的校正因子，并使得该光谱仪能够在其二维电荷耦合器件处产生多个散光光图像 输出。
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公开(公告)号：US4548261A
公开(公告)日：1985-10-22
申请号：US609397
申请日：1984-05-11
CPC分类号： F28F9/02 , F28F9/0239 , F28F9/26 , Y10S165/053
摘要： A recuperative tubular heat exchanger comprised of a plurality of tube-bundle heat exchange modules (20) stacked in a spaced array and interconnected by U-shaped, open-end header conduits (30) to form a serpentine flowpath through which a fluid to be heated is passed in heat exchange relationship with a heating fluid passing in cross flow over the tube bundle modules. The interconnected modules together with the header conduits form an integral assembly which is free to slide on support beams (26) so as to float within the housing (12) of the heat exchanger in response to the thermal deformation of the tube bundle modules.
摘要翻译： 一种换热管式热交换器，包括多个管束热交换模块（20），所述多个管束热交换模块（20）以间隔开的阵列堆叠并且通过U形的开放式总管导管（30）互连，以形成蛇形流动路径 加热的热交换与通过管束模块的交叉流动的加热流体进行热交换。 互连的模块与总管导管一起形成一体的组件，其可在支撑梁（26）上自由滑动，以便响应于管束模块的热变形而浮在热交换器的壳体（12）内。
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公开(公告)号：US4592416A
公开(公告)日：1986-06-03
申请号：US728115
申请日：1985-04-29
申请人： Glenn D. Mattison , Michael A. Case
发明人： Glenn D. Mattison , Michael A. Case
CPC分类号： F28F9/0241 , F28F9/00 , Y10S165/059
摘要： A heat exchange apparatus (10) formed of a plurality of heat exchange modules (20) mounted together in side-by-side relationship to form a box-like array. Each heat exchange module (20) houses a multiplicity of heat exchange tubes (44) which provide a flow passage through which a first heat exchange fluid, such as air, is passed in heat exchange relationship with a second heat exchange fluid, such as flue gas, passing through the heat exchange apparatus over the heat exchange tubes. Each heat exchange module (20) is comprised of a rectangular box-like support frame (30) formed of a pair of spaced apart end frames (32a,32b) interconnected at their respective corners by longitudinally elongated support members (34a,34b), a tube bundle assembly (40) disposed within the support frame, and attachment means (50,50') for mounting the tube bundle assembly to the support frame, the attachment means (50') including expansion means (52) for accommodating translational movement of at least one tube sheet (42a) of the tube bundle assembly within the support frame as the heat exchange tubes of the tube bundle assembly expand or contract longitudinally.
摘要翻译： 一种热交换装置（10），其由多个并排安装在一起的热交换模块（20）形成，形成盒状阵列。 每个热交换模块（20）容纳多个热交换管（44），所述热交换管（44）提供流动通道，第一热交换流体（例如空气）通过该流动通道与第二热交换流体 气体，通过热交换装置通过热交换管。 每个热交换模块（20）包括由一对间隔开的端框架（32a，32b）形成的矩形盒状支撑框架（30），它们在其各自的拐角处由纵向细长的支撑构件（34a，34b）互相连接， 设置在支撑框架内的管束组件（40）和用于将管束组件安装到支撑框架的附接装置（50,50'），附接装置（50'）包括用于容纳平移运动的膨胀装置（52） 当管束组件的热交换管纵向膨胀或收缩时，管束组件的至少一个管板（42a）在支撑框架内。
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