公开(公告)号：US06524913B1

公开(公告)日：2003-02-25

申请号：US10004934

申请日：2001-12-04

申请人： Hung-Sui Lin ,  Han-Chao Lai ,  Tao-Cheng Lu

发明人： Hung-Sui Lin ,  Han-Chao Lai ,  Tao-Cheng Lu

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

摘要： A method of fabricating a non-volatile memory, in which a charge-trapping layer consisting of insulating materials and bar-like conductive layers to be patterned into the gates are formed at first. The buried bit-lines are formed in the substrate between the bar-like conductive layers. Each of the buried bit-lines extends into the substrate under a portion of an adjacent high-K spacer, but not to the substrate under an adjacent bar-like conductive layer. High-K spacers are formed on the side-walls of the bar-like conductive layers. Then the bar-like conductive layers are patterned into the gates, and word-lines are formed on the substrate to electrically connect with the gates. The material of the high-K spacer has a dielectric constant and the high-K spacer has a width, such that a channel will extend to the substrate under the high-K spacer and connect with the buried bit-line when the non-volatile memory is operated.

摘要翻译： 一种制造非易失性存储器的方法，其中首先形成由绝缘材料构成的电荷捕获层和待形成栅格的棒状导电层。 在棒状导电层之间的衬底中形成掩埋位线。 每个埋置的位线在相邻的高K间隔物的一部分下延伸到衬底中，但不延伸到相邻的棒状导电层下方的衬底。 在棒状导电层的侧壁上形成高K隔离物。 然后将棒状导电层图案化成栅极，并且在基板上形成字线以与栅极电连接。 高K间隔物的材料具有介电常数，高K间隔物具有宽度，使得沟道将在高K间隔物下延伸到衬底，并且当非挥发性的时候与掩埋位线连接 内存被操作

公开(公告)号：US06455388B1

公开(公告)日：2002-09-24

申请号：US10099802

申请日：2002-03-13

申请人： Han-Chao Lai ,  Hung-Sui Lin ,  Tao-Cheng Lu

发明人： Han-Chao Lai ,  Hung-Sui Lin ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L21/2652 ,  H01L21/26586 ,  H01L29/665

摘要： A method of fabricating a MOS transistor. First, a substrate having a gate electrode and spacers on the gate electrode sidewalls is provided. A source/drain region is formed in the substrate outside the outer edge of the spacer sidewalls. A self-aligned silicide layer is formed over the exposed surface of the gate electrode and the source/drain regions. A portion of the spacers is removed by etching to form a sharp-angled triangular spacer on the sidewalls of the gate electrode. A pocket implantation of the substrate is carried out to form a pocket region inside the substrate under the side edges of the gate electrode. By controlling the setting of the energy level and the implant angle in the pocket implantation, a precise distribution of the dopants at desired locations within the substrate is reproduced. Finally, the sharp-angled spacers are removed and then a light implantation is conducted to form source/drain extension regions in the substrate on each side of the gate electrode.

摘要翻译： 一种制造MOS晶体管的方法。 首先，提供在栅电极侧壁上具有栅电极和间隔物的基板。 源极/漏极区域形成在衬垫外侧边缘外侧的衬底中。 在栅极电极和源极/漏极区域的暴露表面上形成自对准的硅化物层。 通过蚀刻去除一部分间隔物，以在栅电极的侧壁上形成锐角三角形间隔物。 进行基板的袋式注入，以在栅电极的侧边缘下方的基板内部形成袋区域。 通过控制袋注入中的能级和植入角度的设定，再现了衬底内所需位置处的掺杂剂的精确分布。 最后，去除尖锐的间隔物，然后进行光注入以在栅电极的每一侧上的衬底中形成源极/漏极延伸区域。

公开(公告)号：US06671209B2

公开(公告)日：2003-12-30

申请号：US10035514

申请日：2001-10-22

申请人： Hung-Sui Lin ,  Han-Chao Lai ,  Tao-Cheng Lu

发明人： Hung-Sui Lin ,  Han-Chao Lai ,  Tao-Cheng Lu

IPC分类号： G11C1604

CPC分类号： G11C16/14

摘要： An erasing method for a p-channel nitride read only memory. The method is used for a p-channel nitride read only memory having charges stored in a charge-trapping layer. A positive voltage is applied to the control gate and a negative voltage to the drain; also, the source is floating and the n-well is grounded. The voltage difference between the positive voltage applied to the control gate and the negative voltage to the drain is sufficient to trigger a band-to-band induced hot electron injection to erase the p-channel nitride read only memory.

摘要翻译： 用于p沟道氮化物只读存储器的擦除方法。 该方法用于具有存储在电荷捕获层中的电荷的p沟道氮化物只读存储器。 向控制栅极施加正电压，向漏极施加负电压; 源也是浮动的，n阱是接地的。 施加到控制栅极的正电压和到漏极的负电压之间的电压差足以触发带间感应的热电子注入以擦除p沟道氮化物只读存储器。

公开(公告)号：US06492235B2

公开(公告)日：2002-12-10

申请号：US09770550

申请日：2001-01-26

申请人： Han-Chao Lai ,  Tao-Cheng Lu ,  Hung-Sui Lin

发明人： Han-Chao Lai ,  Tao-Cheng Lu ,  Hung-Sui Lin

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L29/665 ,  H01L29/6653

摘要： A method for forming extension by using double etch spacer. The method includes at least the following steps. First a semiconductor substrate is provided. Then, the gate is formed on the substrate. A first spacer is formed on a sidewall of the gate. Then, numerous first ions are implanted in the substrate by a mask of both the gate and the first spacer to form the source/drain region. Then, the second spacer is formed by etching the first spacer, wherein the width of the second spacer is less than the width of the first spacer. Finally, numerous second ions are implanted in the substrate by a mask of both the gate and the second spacer to form an extension.

摘要翻译： 通过使用双蚀刻间隔物形成延伸的方法。 该方法至少包括以下步骤。 首先提供半导体衬底。 然后，在基板上形成栅极。 第一间隔件形成在栅极的侧壁上。 然后，通过栅极和第一间隔物的掩模将许多第一离子注入到衬底中以形成源极/漏极区。 然后，通过蚀刻第一间隔物形成第二间隔物，其中第二间隔物的宽度小于第一间隔物的宽度。 最后，通过栅极和第二间隔物的掩模将许多第二离子注入到衬底中以形成延伸。

公开(公告)号：US06458643B1

公开(公告)日：2002-10-01

申请号：US09681984

申请日：2001-07-03

申请人： Han-Chao Lai ,  Tao-Cheng Lu ,  Hung-Sui Lin

发明人： Han-Chao Lai ,  Tao-Cheng Lu ,  Hung-Sui Lin

IPC分类号： H01L218238

CPC分类号： H01L29/7833 ,  H01L21/2652 ,  H01L21/324 ,  H01L29/66492 ,  H01L29/6659

摘要： A semiconductor substrate is provided with at least a gate formed on the semiconductor substrate. A first ion implantation process is performed to form a pocket implant region within the semiconductor substrate beneath the gate. Following the first ion implantation process, a first rapid thermal annealing (RTA) process is immediately performed to reduce TED effects resulting from the first ion implantation process. Thereafter, a second implantation process is performed to form a source extension doping region and a drain extension doping region within the semiconductor substrate adjacent to the gate. A source doping region and a drain doping region are then formed within the semiconductor substrate adjacent to the gate. Finally, a second RTA process is performed to simultaneously activate dopants in the source extension doping region, the drain extension doping region, the source doping region and the drain doping region.

摘要翻译： 半导体衬底至少设置有形成在半导体衬底上的栅极。 执行第一离子注入工艺以在栅极下方的半导体衬底内形成凹穴注入区域。 在第一离子注入工艺之后，立即执行第一快速热退火（RTA）工艺以降低由第一离子注入工艺产生的TED效应。 此后，执行第二注入工艺以在与栅极相邻的半导体衬底内形成源极延伸掺杂区域和漏极延伸掺杂区域。 然后在与栅极相邻的半导体衬底内形成源极掺杂区域和漏极掺杂区域。 最后，执行第二RTA工艺以同时激活源延伸掺杂区域，漏极延伸掺杂区域，源极掺杂区域和漏极掺杂区域中的掺杂剂。

公开(公告)号：US06620693B2

公开(公告)日：2003-09-16

申请号：US10055491

申请日：2002-01-22

申请人： Han-Chao Lai ,  Hung-Sui Lin ,  Tao-Cheng Lu

发明人： Han-Chao Lai ,  Hung-Sui Lin ,  Tao-Cheng Lu

IPC分类号： H01L218234

CPC分类号： H01L27/11213 ,  H01L27/105 ,  H01L27/1126 ,  H01L27/11293

摘要： A method for fabricating a non-volatile memory is described. A planar doped region is formed in the substrate at first. A mask layer and a patterned photoresist layer are sequentially formed on the substrate. A plurality of trenches is formed in the substrate with the patterned photoresist layer as a mask to divide the planar doped region into a plurality of bit-lines. The patterned photoresist layer is removed and then a recovering process is performed to recover the side-walls and the bottoms of the trenches from the damages caused by the trench etching step; The mask layer is removed. A dielectric layer is formed on the substrate and then a plurality of word-lines is formed on the dielectric layer.

摘要翻译： 描述了制造非易失性存储器的方法。 首先在衬底中形成平面掺杂区域。 在衬底上依次形成掩模层和图案化的光致抗蚀剂层。 在衬底中形成多个沟槽，其中图案化的光致抗蚀剂层作为掩模将平面掺杂区域分成多个位线。 去除图案化的光致抗蚀剂层，然后执行恢复过程以从沟槽蚀刻步骤引起的损伤中回收沟槽的侧壁和底部; 去除掩模层。 在基板上形成电介质层，然后在电介质层上形成多个字线。

公开(公告)号：US06635946B2

公开(公告)日：2003-10-21

申请号：US09930304

申请日：2001-08-16

申请人： Han-Chao Lai ,  Hung-Sui Lin ,  Tao-Cheng Lu

发明人： Han-Chao Lai ,  Hung-Sui Lin ,  Tao-Cheng Lu

IPC分类号： H01L2976

CPC分类号： H01L29/0649 ,  H01L21/7624 ,  H01L29/66651 ,  H01L29/78654

摘要： A semiconductor device with trench isolation structure is disclosed. The invention uses a trench isolation structure that can be formed by using conventional methods to prevent problems such as drain induced barrier lowering (DIBL), punch-through leakage and spiking leakage. Thus these poor electrical properties of the conventional semiconductor device with a shallow junction depth resulting from the shrink of design rules can be solved.

公开(公告)号：US06524919B2

公开(公告)日：2003-02-25

申请号：US09950215

申请日：2001-09-07

申请人： Han-Chao Lai ,  Hung-Sui Lin ,  Tao-Cheng Lu

发明人： Han-Chao Lai ,  Hung-Sui Lin ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L21/823468 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for manufacturing a metal oxide semiconductor device is provided comprising the steps of: performing an ion implantation to form a source/drain region in the substrate having a gate formed on it and a spacer formed on the sidewalls of the gate; forming a self-aligned silicide layer on the exposed surface of the gate and the source/drain region; removing a portion of the spacer to form a substantially triangular spacer with sharp corners; performing a tilted pocket implantation to form pocket regions within the substrate beside the gate, and controlling the location of the pocket regions and the dopant distribution by adjusting the energy and angle of the tilted pocket implantation; performing a tilted-angle implantation to form a source/drain extension within the substrate beside the gate and underlying the spacer; using the thermal cycle process to adjust the junction depth and the doping profile of the source/drain extension.

摘要翻译： 提供一种制造金属氧化物半导体器件的方法，包括以下步骤：进行离子注入以在其上形成有栅极的基板和形成在栅极的侧壁上的间隔物形成源极/漏极区域; 在栅极和源极/漏极区域的暴露表面上形成自对准的硅化物层; 去除间隔物的一部分以形成具有尖角的基本上三角形的间隔物; 执行倾斜的袋注入以在栅极旁边的衬底内形成袋区，并且通过调整倾斜袋植入的能量和角度来控制袋区的位置和掺杂剂分布; 执行倾斜角度注入以在栅极旁边的衬底内以及衬垫下方形成源极/漏极延伸部; 使用热循环过程来调节源极/漏极延伸的结深度和掺杂分布。

公开(公告)号：US06448142B1

公开(公告)日：2002-09-10

申请号：US09922255

申请日：2001-08-03

申请人： Han-Chao Lai ,  Hung-Sui Lin ,  Tao-Cheng Lu

发明人： Han-Chao Lai ,  Hung-Sui Lin ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L21/2652 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/6653

摘要： A fabrication method for a metal oxide semiconductor transistor is described. A source/drain implantation is conducted on a substrate beside the spacer that is on the sidewall of the gate to form a source/drain region in the substrate beside the spacer. A self-aligned silicide layer is further formed on the gate and the source/drain region. A portion of the spacer is removed to form a triangular spacer with a sharp corner, followed by performing a tilt angle implantation on the substrate to form a source/drain extension region in the substrate under the side of the gate and the spacer with the sharp corner. A thermal cycle is further conducted to adjust the junction depth and the dopant profile of the source/drain extension region.

摘要翻译： 对金属氧化物半导体晶体管的制造方法进行说明。 源极/漏极注入在位于栅极的侧壁上的间隔物旁边的衬底上进行，以在隔板旁边的衬底中形成源极/漏极区域。 在栅极和源极/漏极区域上进一步形成自对准的硅化物层。 去除间隔物的一部分以形成具有锐角的三角形间隔物，随后在衬底上进行倾斜角度注入，以在栅极侧面的衬底中形成源极/漏极延伸区域，并且具有尖锐的衬垫 角。 进一步进行热循环以调节源极/漏极延伸区域的结深度和掺杂物分布。

公开(公告)号：US06808995B2

公开(公告)日：2004-10-26

申请号：US10361681

申请日：2003-02-11

申请人： Hung-Sui Lin ,  Han Chao Lai ,  Tao Cheng Lu

发明人： Hung-Sui Lin ,  Han Chao Lai ,  Tao Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L29/78603 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/66757 ,  H01L29/66772

摘要： A transistor device that includes at least two transistors, each transistor including a source region, a drain region, and a shallow trench isolation formed between and contiguous with the source and drain regions, wherein the shallow trench isolation electrically isolates the source and drain regions to minimize the short-channel effects, a conductor layer disposed over the source region, shallow trench isolation, and drain region, wherein the conductor layer electrically connects the source and drain regions to serve as a channel region, a gate oxide disposed over the conductor layer, and a gate structure formed over the gate oxide.

摘要翻译： 一种晶体管器件，其包括至少两个晶体管，每个晶体管包括在源极和漏极区域之间形成并邻接的源区域，漏极区域和浅沟槽隔离，其中浅沟槽隔离将源极和漏极区域电隔离成 最小化短沟道效应，设置在源极区域上的导体层，浅沟槽隔离和漏极区域，其中导体层将源极和漏极区域电连接以用作沟道区域，设置在导体层上的栅极氧化物 ，以及形成在栅极氧化物上的栅极结构。