公开(公告)号：US07425488B2

公开(公告)日：2008-09-16

申请号：US11245412

申请日：2005-10-05

申请人： Hanming Wu ,  Jiang Zhang ,  John Chen ,  Xian J Ning

发明人： Hanming Wu ,  Jiang Zhang ,  John Chen ,  Xian J Ning

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636

摘要： A partially completed semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device has a gate structure including edges and a substantially pure silicon dioxide mask structure overlying the gate structure. A thickness ranging from about 400 to about 600 Angstroms of the substantially pure silicon dioxide mask structure is included. The device has a dielectric layer forming sidewall spacers on the edges of the gate structure to protect the gate structure including the edges and an exposed portion of the pure silicon dioxide mask structure overlying the gate structure. The device has an epitaxially grown fill material (e.g., silicon/germanium, silicon carbide) in an etched source region and an etched drain region. Preferably, the etched source region and the etched drain region are coupled to the gate structure. The device has a strained channel region between the filled source region and the filled drain region from at least the fill material formed in the etched source region and the etched drain region.

摘要翻译： 部分完成的半导体集成电路器件。 该器件具有覆盖半导体衬底的半导体衬底和电介质层。 该器件具有包括边缘的栅极结构和覆盖栅极结构的基本上纯的二氧化硅掩模结构。 包括约400至约600埃基本上纯的二氧化硅掩模结构的厚度。 器件具有在栅极结构的边缘上形成侧壁间隔物的电介质层，以保护包括边缘的栅极结构和覆盖栅极结构的纯二氧化硅掩模结构的暴露部分。 该器件在蚀刻的源极区域和蚀刻的漏极区域中具有外延生长的填充材料（例如，硅/锗，碳化硅）。 优选地，蚀刻的源极区域和蚀刻的漏极区域耦合到栅极结构。 该装置在填充的源区和填充的漏极区之间具有至少从形成在蚀刻的源极区和蚀刻的漏极区中的填充材料的应变通道区。

公开(公告)号：US08106423B2

公开(公告)日：2012-01-31

申请号：US12145268

申请日：2008-06-24

申请人： Hanming Wu ,  Jiang Zhang ,  John Chen ,  Xian J. Ning

发明人： Hanming Wu ,  Jiang Zhang ,  John Chen ,  Xian J. Ning

IPC分类号： H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636

摘要： A structure using pure silicon dioxide hard marsk for gate pattern. In an embodiment, the present invention provides a partially completed semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device has a gate structure including edges and a substantially pure silicon dioxide mask structure overlying the gate structure. A thickness ranging from about 400 to about 600 Angstroms of the substantially pure silicon dioxide mask structure is included. The device has a dielectric layer forming sidewall spacers on the edges of the gate structure to protect the gate structure including the edges and an exposed portion of the pure silicon dioxide mask structure overlying the gate structure. The device has an epitaxially grown fill material in an etched source region and an etched drain region.

摘要翻译： 一种使用纯二氧化硅硬马尔斯克进行栅极图案的结构。 在一个实施例中，本发明提供了部分完成的半导体集成电路器件。 该器件具有覆盖半导体衬底的半导体衬底和电介质层。 该器件具有包括边缘的栅极结构和覆盖栅极结构的基本上纯的二氧化硅掩模结构。 包括约400至约600埃基本上纯的二氧化硅掩模结构的厚度。 器件具有在栅极结构的边缘上形成侧壁间隔物的电介质层，以保护包括边缘的栅极结构和覆盖栅极结构的纯二氧化硅掩模结构的暴露部分。 该器件在蚀刻源区和蚀刻漏极区中具有外延生长的填充材料。

公开(公告)号：US20090065805A1

公开(公告)日：2009-03-12

申请号：US12145268

申请日：2008-06-24

申请人： Hanming Wu ,  Jiang Zhang ,  John Chen ,  Xian J. Ning

发明人： Hanming Wu ,  Jiang Zhang ,  John Chen ,  Xian J. Ning

IPC分类号： H01L29/78

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636

摘要： A structure using pure silicon dioxide hard marsk for gate pattern. In an embodiment, the present invention provides a partially completed semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device has a gate structure including edges and a substantially pure silicon dioxide mask structure overlying the gate structure. A thickness ranging from about 400 to about 600 Angstroms of the substantially pure silicon dioxide mask structure is included. The device has a dielectric layer forming sidewall spacers on the edges of the gate structure to protect the gate structure including the edges and an exposed portion of the pure silicon dioxide mask structure overlying the gate structure. The device has an epitaxially grown fill material in an etched source region and an etched drain region.

摘要翻译： 一种使用纯二氧化硅硬马尔斯克进行栅极图案的结构。 在一个实施例中，本发明提供了部分完成的半导体集成电路器件。 该器件具有覆盖半导体衬底的半导体衬底和电介质层。 该器件具有包括边缘的栅极结构和覆盖栅极结构的基本上纯的二氧化硅掩模结构。 包括约400至约600埃基本上纯的二氧化硅掩模结构的厚度。 器件具有在栅极结构的边缘上形成侧壁间隔物的电介质层，以保护包括边缘的栅极结构和覆盖栅极结构的纯二氧化硅掩模结构的暴露部分。 该器件在蚀刻源区和蚀刻漏极区中具有外延生长的填充材料。

公开(公告)号：US07709336B2

公开(公告)日：2010-05-04

申请号：US11321767

申请日：2005-12-28

申请人： Xian J. Ning ,  Hanming Wu ,  John Chen

发明人： Xian J. Ning ,  Hanming Wu ,  John Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/3081 ,  H01L21/32139 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device also has a gate structure including edges. A metal hard mask layer is overlying the gate structure. A dielectric layer is formed sidewall spacers on the edges of the gate structure to protect the gate structure including the edges. An exposed portion of the metal hard mask layer is overlying the gate structure. A silicon germanium fill material is provided in an etched source region and an etched drain region. The etched source region and the etched drain region are each coupled to the gate structure. The device has a strained channel region between the filled source region and the filled drain region from at least the silicon germanium material formed in the etched source region and the etched drain region. An electrical connection is coupled to the metal hard mask overlying the gate structure. Optionally, the device has a second metal layer overlying the metal hard mask.

摘要翻译： 半导体集成电路器件。 该器件具有覆盖半导体衬底的半导体衬底和电介质层。 该装置还具有包括边缘的门结构。 金属硬掩模层覆盖栅极结构。 电介质层在门结构的边缘上形成侧墙，以保护包括边缘的栅结构。 金属硬掩模层的暴露部分覆盖栅极结构。 在蚀刻源区域和蚀刻漏极区域中提供硅锗填充材料。 蚀刻的源极区域和蚀刻的漏极区域各自耦合到栅极结构。 该器件在至少形成在蚀刻源极区域和蚀刻漏极区域中的硅锗材料之间具有在填充源极区域和填充的漏极区域之间的应变通道区域。 电连接耦合到覆盖栅极结构的金属硬掩模。 可选地，该装置具有覆盖金属硬掩模的第二金属层。

公开(公告)号：US07591659B2

公开(公告)日：2009-09-22

申请号：US11243707

申请日：2005-10-04

申请人： John Chen ,  Xian J. Ning ,  Hanming Wu

发明人： John Chen ,  Xian J. Ning ,  Hanming Wu

IPC分类号： H01L21/8238

CPC分类号： H01L29/66545 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for forming a CMOS semiconductor wafer. The method includes providing a semiconductor substrate (e.g., silicon wafer) and forming a dielectric layer (e.g., silicon dioxide, silicon oxynitride) overlying the semiconductor substrate. The method includes forming a gate layer overlying the dielectric layer and patterning the gate layer to form a gate structure including edges. The method includes forming a dielectric layer overlying the gate structure to protect the gate structure including the edges. Preferably, the dielectric layer has a thickness of less than 40 nanometers. The method includes etching a source region and a drain region adjacent to the gate structure using the dielectric layer as a protective layer and depositing silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region. The method causes a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region. The method includes forming a second protective layer overlying surfaces and performing an anisotropic etching process to form spacer structures to seal the gate structure.

摘要翻译： 一种用于形成CMOS半导体晶片的方法。 该方法包括提供半导体衬底（例如硅晶片）并形成覆盖半导体衬底的电介质层（例如，二氧化硅，氮氧化硅）。 该方法包括形成覆盖在介电层上的栅极层，并构图栅极层以形成包括边缘的栅极结构。 该方法包括形成覆盖栅极结构的电介质层，以保护包括边缘的栅极结构。 优选地，电介质层的厚度小于40纳米。 该方法包括使用电介质层作为保护层蚀刻与栅极结构相邻的源极区域和漏极区域，并将硅锗材料沉积到源极区域和漏极区域中以填充蚀刻的源极区域和蚀刻的漏极区域。 该方法使得源极区域和漏极区域之间的沟道区域至少在形成于源极区域和漏极区域中的硅锗材料以压缩模式应变。 该方法包括形成覆盖表面的第二保护层，并执行各向异性蚀刻工艺以形成间隔结构以密封栅极结构。

公开(公告)号：US20070063221A1

公开(公告)日：2007-03-22

申请号：US11245412

申请日：2005-10-05

申请人： Hanming Wu ,  Jiang Zhang ,  John Chen ,  Xian Ning

发明人： Hanming Wu ,  Jiang Zhang ,  John Chen ,  Xian Ning

IPC分类号： H01L31/00

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636

摘要： A partially completed semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device has a gate structure including edges and a substantially pure silicon dioxide mask structure overlying the gate structure. A thickness ranging from about 400 to about 600 Angstroms of the substantially pure silicon dioxide mask structure is included. The device has a dielectric layer forming sidewall spacers on the edges of the gate structure to protect the gate structure including the edges and an exposed portion of the pure silicon dioxide mask structure overlying the gate structure. The device has an epitaxially grown fill material (e.g., silicon/germanium, silicon carbide) in an etched source region and an etched drain region. Preferably, the etched source region and the etched drain region are coupled to the gate structure. The device has a strained channel region between the filled source region and the filled drain region from at least the fill material formed in the etched source region and the etched drain region.

摘要翻译： 部分完成的半导体集成电路器件。 该器件具有覆盖半导体衬底的半导体衬底和电介质层。 该器件具有包括边缘的栅极结构和覆盖栅极结构的基本上纯的二氧化硅掩模结构。 包括约400至约600埃基本上纯的二氧化硅掩模结构的厚度。 器件具有在栅极结构的边缘上形成侧壁间隔物的电介质层，以保护包括边缘的栅极结构和覆盖栅极结构的纯二氧化硅掩模结构的暴露部分。 该器件在蚀刻的源极区域和蚀刻的漏极区域中具有外延生长的填充材料（例如，硅/锗，碳化硅）。 优选地，蚀刻的源极区域和蚀刻的漏极区域耦合到栅极结构。 该装置在填充的源区和填充的漏极区之间具有至少从形成在蚀刻的源极区和蚀刻的漏极区中的填充材料的应变通道区。

公开(公告)号：US08466050B2

公开(公告)日：2013-06-18

申请号：US12830241

申请日：2010-07-02

申请人： Hanming Wu ,  Chia Hao Lee ,  John Chen

发明人： Hanming Wu ,  Chia Hao Lee ,  John Chen

IPC分类号： H01L21/425

CPC分类号： H01J37/3171 ,  H01J37/3007 ,  H01J2237/055 ,  H01J2237/0825 ,  H01L21/2236 ,  H01L21/26513 ,  H01L29/0847 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for forming a lightly doped drain (LDD) region in a semiconductor substrate. The method includes generating an ion beam of a selected species, and accelerating the ion beam, wherein the accelerated ion beam includes a first accelerated portion and a second accelerated portion. The method further includes deflecting the accelerating ion beam, wherein the first and second accelerated portions are concurrently deflected into a first path trajectory having a first deflected angle and second path trajectory having a second deflected angle. In an embodiment, the first and second path trajectories travel in the same direction, which is perpendicular to the surface region of the semiconductor wafer, and the first deflected angle is greater than the second deflected angle. In an embodiment, the selected species may include an n-type ion comprising phosphorous (P), arsenic (As), or antimony (Sb).

摘要翻译： 一种在半导体衬底中形成轻掺杂漏极（LDD）区域的方法。 该方法包括产生所选物种的离子束并加速离子束，其中加速离子束包括第一加速部分和第二加速部分。 该方法还包括偏转加速离子束，其中第一和第二加速部分同时偏转到具有第一偏转角的第一路径轨迹和具有第二偏转角的第二路径轨迹。 在一个实施例中，第一和第二路径轨迹在与半导体晶片的表面区域垂直的相同方向上行进，并且第一偏转角度大于第二偏转角度。 在一个实施方案中，所选择的物质可​​以包括包含磷（P），砷（As）或锑（Sb）的n型离子。

公开(公告)号：US20080173941A1

公开(公告)日：2008-07-24

申请号：US11678582

申请日：2007-02-24

申请人： Bei Zhu ,  Paolo Bonfanti ,  Hanming Wu ,  Da Wei Gao ,  John Chen

发明人： Bei Zhu ,  Paolo Bonfanti ,  Hanming Wu ,  Da Wei Gao ,  John Chen

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor integrated circuit device comprising a semiconductor substrate, e.g., silicon wafer, silicon on insulator. The device has a dielectric layer overlying the semiconductor substrate and a gate structure overlying the dielectric layer. The device also has a channel region within a portion of the semiconductor substrate within a vicinity of the gate structure and a lightly doped source/drain regions in the semiconductor substrate to from diffused pocket regions underlying portions of the gate structure. The device has sidewall spacers on edges of the gate structure. The device also has an etched source region and an etched drain region. Each of the first source region and the first drain region is characterized by a recessed region having substantially vertical walls, a bottom region, and rounded corner regions connecting the vertical walls to the bottom region.

摘要翻译： 一种半导体集成电路器件，包括半导体衬底，例如硅晶片，绝缘体上硅。 该器件具有覆盖半导体衬底的电介质层和覆盖该介电层的栅极结构。 器件还在栅极结构附近的半导体衬底的一部分内部具有通道区域，以及半导体衬底中的轻掺杂源极/漏极区域，以从栅极结构的部分下方的扩散袋区域。 该装置在栅极结构的边缘上具有侧壁间隔物。 该器件还具有蚀刻源极区和蚀刻漏极区。 第一源极区域和第一漏极区域中的每一个的特征在于具有基本上垂直的壁的凹陷区域，底部区域和将垂直壁连接到底部区域的圆角区域。

公开(公告)号：US20080119032A1

公开(公告)日：2008-05-22

申请号：US11609748

申请日：2006-12-12

申请人： John Chen ,  Hanming Wu ,  Da Wei Gao ,  Bei Zhu ,  Paolo Bonfanti

发明人： John Chen ,  Hanming Wu ,  Da Wei Gao ,  Bei Zhu ,  Paolo Bonfanti

IPC分类号： H01L21/3205

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  Y10S438/938

摘要： A method for forming an strained silicon integrated circuit device. The method includes providing a semiconductor substrate and forming a dielectric layer overlying the semiconductor substrate. The method also includes forming a gate layer overlying the dielectric layer and forming a hard mask overlying the gate layer. The method patterns the gate layer to form a gate structure including edges using the hard mask as a protective layer. The method forms a dielectric layer overlying the gate structure to protect the gate structure including the edges. The method forms spacers from the dielectric layer, while maintaining the hard mask overlying the gate structure. The method etches a source region and a drain region adjacent to the gate structure using the dielectric layer and the hard mask as a protective layer, while the hard mask prevents any portion of the gate structure from being exposed. In a preferred embodiment, the method maintains the hard mask overlying the gate structure. The method includes depositing silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region, while maintaining any portion of the gate layer from being exposed using the hard mask such that the gate structure is substantially free from any permanent deposition of silicon germanium material, which causes a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region. In a preferred embodiment, the method removing the hard mask from the gate structure to expose a top portion of the gate structure and maintains the top portion of the gate structure being substantially free from any silicon germanium material.

摘要翻译： 一种形成应变硅集成电路器件的方法。 该方法包括提供半导体衬底并形成覆盖半导体衬底的电介质层。 该方法还包括形成覆盖在电介质层上的栅极层，并形成覆盖栅极层的硬掩模。 该方法使栅极层形成包括使用硬掩模的边缘作为保护层的栅极结构。 该方法形成覆盖栅极结构的电介质层，以保护包括边缘的栅极结构。 该方法从电介质层形成间隔物，同时保持覆盖栅极结构的硬掩模。 该方法使用电介质层和硬掩模作为保护层来蚀刻与栅极结构相邻的源极区域和漏极区域，同时硬掩模防止栅极结构的任何部分暴露。 在优选实施例中，该方法保持覆盖栅极结构的硬掩模。 该方法包括将硅锗材料沉积到源极区域和漏极区域中以填充蚀刻的源极区域和蚀刻的漏极区域，同时保持栅极层的任何部分不被使用硬掩模曝光，使得栅极结构基本上是空的 来自硅锗材料的任何永久性沉积，其使得源极区域和漏极区域之间的沟道区域至少在形成于源极区域和漏极区域中的硅锗材料以压缩模式应变。 在优选实施例中，该方法从栅极结构去除硬掩模以露出栅极结构的顶部并且保持栅极结构的顶部基本上不含任何硅锗材料。

公开(公告)号：US20060194395A1

公开(公告)日：2006-08-31

申请号：US11321767

申请日：2005-12-28

申请人： Xian Ning ,  Hanming Wu ,  John Chen

发明人： Xian Ning ,  Hanming Wu ,  John Chen

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L29/7848 ,  H01L21/3081 ,  H01L21/32139 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device also has a gate structure including edges. A metal hard mask layer is overlying the gate structure. A dielectric layer is formed sidewall spacers on the edges of the gate structure to protect the gate structure including the edges. An exposed portion of the metal hard mask layer is overlying the gate structure. A silicon germanium fill material is provided in an etched source region and an etched drain region. The etched source region and the etched drain region are each coupled to the gate structure. The device has a strained channel region between the filled source region and the filled drain region from at least the silicon germanium material formed in the etched source region and the etched drain region. An electrical connection is coupled to the metal hard mask overlying the gate structure. Optionally, the device has a second metal layer overlying the metal hard mask.

摘要翻译： 半导体集成电路器件。 该器件具有覆盖半导体衬底的半导体衬底和电介质层。 该装置还具有包括边缘的门结构。 金属硬掩模层覆盖栅极结构。 电介质层在门结构的边缘上形成侧墙，以保护包括边缘的栅结构。 金属硬掩模层的暴露部分覆盖栅极结构。 在蚀刻源区域和蚀刻漏极区域中提供硅锗填充材料。 蚀刻的源极区域和蚀刻的漏极区域各自耦合到栅极结构。 该器件在至少形成在蚀刻源极区域和蚀刻漏极区域中的硅锗材料之间具有在填充源极区域和填充的漏极区域之间的应变通道区域。 电连接耦合到覆盖栅极结构的金属硬掩模。 可选地，该装置具有覆盖金属硬掩模的第二金属层。