公开(公告)号：US07709336B2

公开(公告)日：2010-05-04

申请号：US11321767

申请日：2005-12-28

申请人： Xian J. Ning ,  Hanming Wu ,  John Chen

发明人： Xian J. Ning ,  Hanming Wu ,  John Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/3081 ,  H01L21/32139 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device also has a gate structure including edges. A metal hard mask layer is overlying the gate structure. A dielectric layer is formed sidewall spacers on the edges of the gate structure to protect the gate structure including the edges. An exposed portion of the metal hard mask layer is overlying the gate structure. A silicon germanium fill material is provided in an etched source region and an etched drain region. The etched source region and the etched drain region are each coupled to the gate structure. The device has a strained channel region between the filled source region and the filled drain region from at least the silicon germanium material formed in the etched source region and the etched drain region. An electrical connection is coupled to the metal hard mask overlying the gate structure. Optionally, the device has a second metal layer overlying the metal hard mask.

摘要翻译： 半导体集成电路器件。 该器件具有覆盖半导体衬底的半导体衬底和电介质层。 该装置还具有包括边缘的门结构。 金属硬掩模层覆盖栅极结构。 电介质层在门结构的边缘上形成侧墙，以保护包括边缘的栅结构。 金属硬掩模层的暴露部分覆盖栅极结构。 在蚀刻源区域和蚀刻漏极区域中提供硅锗填充材料。 蚀刻的源极区域和蚀刻的漏极区域各自耦合到栅极结构。 该器件在至少形成在蚀刻源极区域和蚀刻漏极区域中的硅锗材料之间具有在填充源极区域和填充的漏极区域之间的应变通道区域。 电连接耦合到覆盖栅极结构的金属硬掩模。 可选地，该装置具有覆盖金属硬掩模的第二金属层。

公开(公告)号：US08106423B2

公开(公告)日：2012-01-31

申请号：US12145268

申请日：2008-06-24

申请人： Hanming Wu ,  Jiang Zhang ,  John Chen ,  Xian J. Ning

发明人： Hanming Wu ,  Jiang Zhang ,  John Chen ,  Xian J. Ning

IPC分类号： H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636

摘要： A structure using pure silicon dioxide hard marsk for gate pattern. In an embodiment, the present invention provides a partially completed semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device has a gate structure including edges and a substantially pure silicon dioxide mask structure overlying the gate structure. A thickness ranging from about 400 to about 600 Angstroms of the substantially pure silicon dioxide mask structure is included. The device has a dielectric layer forming sidewall spacers on the edges of the gate structure to protect the gate structure including the edges and an exposed portion of the pure silicon dioxide mask structure overlying the gate structure. The device has an epitaxially grown fill material in an etched source region and an etched drain region.

摘要翻译： 一种使用纯二氧化硅硬马尔斯克进行栅极图案的结构。 在一个实施例中，本发明提供了部分完成的半导体集成电路器件。 该器件具有覆盖半导体衬底的半导体衬底和电介质层。 该器件具有包括边缘的栅极结构和覆盖栅极结构的基本上纯的二氧化硅掩模结构。 包括约400至约600埃基本上纯的二氧化硅掩模结构的厚度。 器件具有在栅极结构的边缘上形成侧壁间隔物的电介质层，以保护包括边缘的栅极结构和覆盖栅极结构的纯二氧化硅掩模结构的暴露部分。 该器件在蚀刻源区和蚀刻漏极区中具有外延生长的填充材料。

公开(公告)号：US07591659B2

公开(公告)日：2009-09-22

申请号：US11243707

申请日：2005-10-04

申请人： John Chen ,  Xian J. Ning ,  Hanming Wu

发明人： John Chen ,  Xian J. Ning ,  Hanming Wu

IPC分类号： H01L21/8238

CPC分类号： H01L29/66545 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for forming a CMOS semiconductor wafer. The method includes providing a semiconductor substrate (e.g., silicon wafer) and forming a dielectric layer (e.g., silicon dioxide, silicon oxynitride) overlying the semiconductor substrate. The method includes forming a gate layer overlying the dielectric layer and patterning the gate layer to form a gate structure including edges. The method includes forming a dielectric layer overlying the gate structure to protect the gate structure including the edges. Preferably, the dielectric layer has a thickness of less than 40 nanometers. The method includes etching a source region and a drain region adjacent to the gate structure using the dielectric layer as a protective layer and depositing silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region. The method causes a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region. The method includes forming a second protective layer overlying surfaces and performing an anisotropic etching process to form spacer structures to seal the gate structure.

摘要翻译： 一种用于形成CMOS半导体晶片的方法。 该方法包括提供半导体衬底（例如硅晶片）并形成覆盖半导体衬底的电介质层（例如，二氧化硅，氮氧化硅）。 该方法包括形成覆盖在介电层上的栅极层，并构图栅极层以形成包括边缘的栅极结构。 该方法包括形成覆盖栅极结构的电介质层，以保护包括边缘的栅极结构。 优选地，电介质层的厚度小于40纳米。 该方法包括使用电介质层作为保护层蚀刻与栅极结构相邻的源极区域和漏极区域，并将硅锗材料沉积到源极区域和漏极区域中以填充蚀刻的源极区域和蚀刻的漏极区域。 该方法使得源极区域和漏极区域之间的沟道区域至少在形成于源极区域和漏极区域中的硅锗材料以压缩模式应变。 该方法包括形成覆盖表面的第二保护层，并执行各向异性蚀刻工艺以形成间隔结构以密封栅极结构。

公开(公告)号：US20090065805A1

公开(公告)日：2009-03-12

申请号：US12145268

申请日：2008-06-24

申请人： Hanming Wu ,  Jiang Zhang ,  John Chen ,  Xian J. Ning

发明人： Hanming Wu ,  Jiang Zhang ,  John Chen ,  Xian J. Ning

IPC分类号： H01L29/78

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636

摘要： A structure using pure silicon dioxide hard marsk for gate pattern. In an embodiment, the present invention provides a partially completed semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device has a gate structure including edges and a substantially pure silicon dioxide mask structure overlying the gate structure. A thickness ranging from about 400 to about 600 Angstroms of the substantially pure silicon dioxide mask structure is included. The device has a dielectric layer forming sidewall spacers on the edges of the gate structure to protect the gate structure including the edges and an exposed portion of the pure silicon dioxide mask structure overlying the gate structure. The device has an epitaxially grown fill material in an etched source region and an etched drain region.

摘要翻译： 一种使用纯二氧化硅硬马尔斯克进行栅极图案的结构。 在一个实施例中，本发明提供了部分完成的半导体集成电路器件。 该器件具有覆盖半导体衬底的半导体衬底和电介质层。 该器件具有包括边缘的栅极结构和覆盖栅极结构的基本上纯的二氧化硅掩模结构。 包括约400至约600埃基本上纯的二氧化硅掩模结构的厚度。 器件具有在栅极结构的边缘上形成侧壁间隔物的电介质层，以保护包括边缘的栅极结构和覆盖栅极结构的纯二氧化硅掩模结构的暴露部分。 该器件在蚀刻源区和蚀刻漏极区中具有外延生长的填充材料。

公开(公告)号：US08158520B2

公开(公告)日：2012-04-17

申请号：US10969886

申请日：2004-10-20

申请人： Xian J. Ning

发明人： Xian J. Ning

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An integrated circuit device structure with a novel contact feature. The structure includes a substrate, a dielectric layer overlying the substrate, and a metal interconnect overlying the dielectric layer. A first interlayer dielectric layer is formed surrounding the metal interconnect. A second interlayer dielectric layer of a predetermined thickness is overlying the first interlayer dielectric layer. A trench opening of a first width is formed within an upper portion of the second interlayer dielectric layer. A first barrier layer is within and is overlying the trench opening of the first width. A contact opening of a second width is within a lower portion of the second interlayer dielectric layer. The second width is less than the first width. The lower portion of the second interlayer dielectric layer is coupled to the upper portion of the second interlayer dielectric layer within the predetermined thickness of the second interlayer dielectric. A second barrier layer is within and is overlying the opening of the contact opening and overlying the first barrier layer. A directional partially or completely removal of the second barrier forming a low contact resistance structure. A copper material is formed overlying the first barrier layer and the second barrier layer to substantially fill the contact opening and the trench within the second interlayer dielectric layer.

摘要翻译： 具有新颖接触特征的集成电路器件结构。 该结构包括衬底，覆盖衬底的电介质层和覆盖在电介质层上的金属互连。 形成围绕金属互连的第一层间介质层。 具有预定厚度的第二层间介质层覆盖在第一层间介电层上。 在第二层间电介质层的上部形成有第一宽度的沟槽开口。 第一阻挡层位于第一宽度的沟槽开口内并且覆盖第一宽度的沟槽开口。 第二宽度的接触开口在第二层间电介质层的下部内。 第二宽度小于第一宽度。 第二层间电介质层的下部在第二层间电介质的预定厚度内耦合到第二层间电介质层的上部。 第二阻挡层位于接触开口的开口内并且覆盖在第一阻挡层上方。 定向部分地或完全地去除形成低接触电阻结构的第二阻挡层。 形成覆盖在第一阻挡层和第二阻挡层上的铜材料，以基本上填充第二层间电介质层内的接触开口和沟槽。

公开(公告)号：US07479699B2

公开(公告)日：2009-01-20

申请号：US11611391

申请日：2006-12-15

申请人： Xian J. Ning

发明人： Xian J. Ning

IPC分类号： H01L23/48

CPC分类号： H01L23/585 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques for an integrated circuit device are provided. The integrated circuit device includes a semiconductor substrate, an integrated circuit, a dielectric layer, and a sealing structure. The sealing structure surrounds the integrated circuit and is disposed within the dielectric layer to prevent damage to the integrated circuit. The sealing structure includes a plurality of metal traces organized in vertical layers and a plurality of vias. Each via of the plurality of vias couples at least two metal traces of the plurality of metal traces from adjacent vertical layers. Each via of the plurality of vias contacts at least two orthogonal surfaces of a lower metal trace of the at least two metal traces. The plurality of metal traces and plurality of vias form a continuous boundary.

摘要翻译： 提供了一种用于集成电路器件的技术。 集成电路器件包括半导体衬底，集成电路，电介质层和密封结构。 密封结构围绕集成电路并且设置在介电层内以防止对集成电路的损坏。 密封结构包括以垂直层和多个通孔组织的多个金属迹线。 多个通孔的每个通孔将多个金属迹线中的至少两个金属迹线与相邻的垂直层耦合。 多个通孔的每个通孔接触至少两个金属迹线的下部金属迹线的至少两个正交表面。 多个金属迹线和多个通孔形成连续的边界。

公开(公告)号：US20080142975A1

公开(公告)日：2008-06-19

申请号：US11611332

申请日：2006-12-15

申请人： Xian J. Ning

发明人： Xian J. Ning

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76801 ,  H01L23/522 ,  H01L23/53228 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device. The method includes providing a semiconductor substrate including a surface region. The method forms a first interlayer dielectric overlying the surface region and forms an interconnect layer overlying the first interlayer dielectric layer. The method also forms a low K dielectric layer overlying the interconnect layer, which has a predetermined shape. The method forms a copper interconnect layer overlying the low K dielectric layer. In a preferred embodiment, the low K dielectric layer maintains the predetermined shape using a dummy pattern structure provided within a portion of the low K dielectric layer to mechanically support and maintain the predetermined shape of the low K dielectric layer between the interconnect layer and the copper interconnect layer.

摘要翻译： 一种半导体器件的制造方法。 该方法包括提供包括表面区域的半导体衬底。 该方法形成覆盖表面区域的第一层间电介质，并形成覆盖第一层间介质层的互连层。 该方法还形成了覆盖互连层的低K电介质层，其具有预定的形状。 该方法形成覆盖在低K电介质层上的铜互连层。 在优选实施例中，低K电介质层使用设置在低K电介质层的一部分内的虚设图案结构来保持预定形状，以在互连层和铜之间机械地支撑和保持低K电介质层的预定形状 互连层。

公开(公告)号：US06979526B2

公开(公告)日：2005-12-27

申请号：US10161867

申请日：2002-06-03

申请人： Xian J. Ning

发明人： Xian J. Ning

IPC分类号： G03F7/20 ,  G03F9/00 ,  G03F7/40 ,  H01L21/00 ,  H01L21/20 ,  H01L21/311

CPC分类号： G03F9/708 ,  G03F7/70633 ,  G03F9/7084 ,  H01L27/222 ,  H01L43/12

摘要： A method of manufacturing a resistive semiconductor memory device (10), comprising depositing an insulating layer (34) over a workpiece (30), and defining a pattern for a plurality of alignment marks (22) and a plurality of conductive lines (54) within the insulating layer (34). A resist (50) is formed over the alignment marks (22), and a conductive material (52) is deposited over the wafer to fill the conductive pattern. The wafer is chemically-mechanically polished to remove excess conductive material from over the insulating layer and form conductive lines (54). The resist (50) is removed from over the alignment marks (22), and the alignment marks (22) are used for alignment of subsequently deposited layers of the resistive memory device (10).

摘要翻译： 一种制造电阻半导体存储器件（10）的方法，包括在工件（30）上沉积绝缘层（34），并且限定多个对准标记（22）和多条导线（54）的图案， 在绝缘层（34）内。 在对准标记（22）之上形成抗蚀剂（50），并且导电材料（52）沉积在晶片上以填充导电图案。 晶片被化学机械抛光以从绝缘层上方去除多余的导电材料并形成导电线（54）。 从对准标记（22）上方去除抗蚀剂（50），并且对准标记（22）用于电阻式存储器件（10）的后续沉积层的对准。

公开(公告)号：US06960365B2

公开(公告)日：2005-11-01

申请号：US10057575

申请日：2002-01-25

申请人： Xian J. Ning

发明人： Xian J. Ning

IPC分类号： H01L21/02 ,  H01L27/08 ,  B05D5/12 ,  H01L21/20 ,  H01L29/00

CPC分类号： H01L28/60 ,  H01L27/0805 ,  H01L28/55 ,  H01L28/75 ,  H01L28/91

摘要： A method of manufacturing a vertical metal-insulator-metal capacitor (MIMCap) (10) in regions (19) of an insulating layer (14). Trenches for both conductive lines and vertical MIMCap's are formed in the insulating layer (14), and regions (19) are covered by resist (20) while the conductive lines (24) are deposited on the wafer. The resist (20) is removed, and the MIMCap dielectric and top plate conductive material (28) is deposited, forming a vertical MIMCap in regions (19).

摘要翻译： 一种在绝缘层（14）的区域（19）中制造垂直金属 - 绝缘体 - 金属电容器（MIMCap）（10）的方法。 在绝缘层（14）中形成用于导电线和垂直MIMCap的沟槽，并且当导电线（24）沉积在晶片上时，区域（19）被抗蚀剂（20）覆盖。 去除抗蚀剂（20），并且沉积MIMCap电介质和顶板导电材料（28），在区域（19）中形成垂直MIMCap。

公开(公告)号：US06635496B2

公开(公告)日：2003-10-21

申请号：US09977027

申请日：2001-10-12

申请人： Xian J. Ning

发明人： Xian J. Ning

IPC分类号： H01L2100

CPC分类号： H01L27/222 ,  H01L43/12

摘要： A method of fabricating an MRAM device includes patterning a magnetic stack material layer (142) using a herd mask (146) formed by a “plate-through” technique. A resist (144) is deposited over magnetic stack material (142), and the resist (144) is patterned, exposing regions of the magnetic stack material (142). A hard mask (146) is formed over the magnetic stack material (142) exposed regions through the resist (144), and the hard mask (146) is used to pattern magnetic tunnel junctions (MTJ's) of the MRAM device. Electroplating, electro-less plating, sputtering, physical vapor deposition (PVD), evaporation deposition, or combinations thereof are used to deposit a material comprising a metal over the magnetic stack material (142) exposed regions to form the hard mask (146).

摘要翻译： 一种制造MRAM器件的方法包括使用由“平板”技术形成的群体掩模（146）图案化磁性堆叠材料层（142）。 抗蚀剂（144）沉积在磁性堆叠材料（142）上，并且对抗蚀剂（144）进行图案化，暴露磁性堆叠材料（142）的区域。 在磁性堆叠材料（142）上形成通过抗蚀剂（144）的暴露区域的硬掩模（146），并且硬掩模（146）用于对MRAM器件的磁性隧道结（MTJ）进行图案化。 使用电镀，无电镀，溅射，物理气相沉积（PVD），蒸发沉积或其组合以将包含金属的材料沉积在磁性堆叠材料（142）暴露区域上以形成硬掩模（146）。