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1.发明授权method for providing automatic adaptation to frequency offsets in high speed serial links 有权用于在高速串行链路中提供自动适应频率偏移的方法公开(公告)号：US07477713B2
公开(公告)日：2009-01-13
申请号：US10791175
申请日：2004-03-02
申请人： Hayden C. Cranford, Jr. , Gareth John Nicholls , Bobak Modaress-Razavi , Vernon R. Norman , Martin L. Schmatz
发明人： Hayden C. Cranford, Jr. , Gareth John Nicholls , Bobak Modaress-Razavi , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H04L7/02
CPC分类号： H03L7/0814 , H03L7/07 , H04L2027/0065 , H04L2027/0067
摘要： Aspects of providing automatic adaptation to frequency offsets in high speed serial links are described. First signals for phase adjusts in a receiver link are adjusted by detecting trends in the first signals to generate second signals, the second signals improving a rate of compensation for the frequency offsets by the phase adjusts. An up/down counter is included for counting signals for phase adjustments by a clock-data-recovery loop of a serial receiver. An adder is coupled to the up/down counter and outputs accumulated data indicative of a trend in the phase adjustments. Combinatorial logic coupled to the adder adapts the signals based on the accumulated data.
摘要翻译： 描述了在高速串行链路中提供对频偏的自动适配的方面。 通过检测第一信号中的趋势来产生第二信号来调整在接收机链路中进行相位调整的第一信号，第二信号通过相位调整来提高对频偏的补偿率。 包括一个向上/向下计数器，用于通过串行接收器的时钟数据恢复环来对信号进行相位调整。 加法器耦合到上/下计数器并输出指示相位调整趋势的累加数据。 耦合到加法器的组合逻辑基于累积数据来适配信号。
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2.发明授权One-sample-per-bit decision feedback equalizer (DFE) clock and data recovery 失效单采样每位决策反馈均衡器（DFE）时钟和数据恢复公开(公告)号：US07809054B2
公开(公告)日：2010-10-05
申请号：US11405997
申请日：2006-04-18
申请人： Juan A. Carballo , Hayden C. Cranford, Jr. , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
发明人： Juan A. Carballo , Hayden C. Cranford, Jr. , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
CPC分类号： H04L25/03063
摘要： Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a decision feedback equalizer along with the appropriate (CDR) loop phase detector to maintain a single sample per bit requirement. The incoming voltage is converted to a current and connected to a current summing node. Weighted currents determined by the values of previously detected bits and their respective feedback coefficients are also connected to this node. Additionally, the summed currents is integrated and converted to a voltage. A sampler is utilized to make a bit decision based on the resulting voltage. After sampling, the integrator is reset before analysis of the next bit. The necessary amplification is achieved by maximizing the sensitivity of the latch, using integration in front of the data latch.
摘要翻译： 公开了一种在接收机中利用/产生一个每位采样的判决反馈均衡器（DFE）时钟和数据恢复（CDR）架构的接收器电路，方法和设计架构，并且降低了误码率（BER ）。 集成接收机与决策反馈均衡器以及适当的（CDR）环路相位检测器相结合，以保持每位需求的单个采样。 输入电压被转换为电流并连接到电流求和节点。 由先前检测到的位及其各自的反馈系数的值确定的加权电流也连接到该节点。 另外，总和电流被积分并转换成电压。 采样器用于基于所得到的电压进行位决定。 采样后，积分器在分析下一位之前被复位。 通过使用在数据锁存器前面的积分来最大化锁存器的灵敏度来实现必要的放大。
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公开(公告)号：US07661052B2
公开(公告)日：2010-02-09
申请号：US12021950
申请日：2008-01-29
IPC分类号： G06F11/277 , G06F11/16
CPC分类号： G01R31/31901 , G01R31/31707
摘要： A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.
摘要翻译： 公开了一种用于测试高速电路的方法和系统。 该方法和系统包括使用常规测试仪获得高速电路的高速统计特征。 该方法和系统还包括将高速电路的高速统计签名与预期签名进行比较。 因此，可以确定高速电路是否在期望的参数内起作用。
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公开(公告)号：US07512177B2
公开(公告)日：2009-03-31
申请号：US11828390
申请日：2007-07-26
IPC分类号： H04B3/46
CPC分类号： H04L25/068 , H04B3/462 , H04L1/205
摘要： Apparatuses and methods comprise a phase shifter, an adjustable capacitance configured to adjust a phase shift of said phase shifter, an arbitrary waveform generator configured to adjust the adjustable capacitance, and a pulse pattern generator coupled to the phase shifter, the phase shifter is configured to control the pulse pattern generator. In one aspect, an adjustable capacitance is at least one varactor diode. In another, a pair of varactor diodes are separated by λ/4 lines, an input and an output of the adjustable capacitance is AC-coupled, and the arbitrary waveform generator is configured to adjust the adjustable capacitance through a gaussian noise signal input to the pair of varactor diodes. A deterministic jitter generator may be coupled to the pulse pattern generator. An open-circuited stub line may be input to the pattern generator, a deterministic jitter content number adjustable varying stub line length.
摘要翻译： 装置和方法包括移相器，被配置为调整所述移相器的相移的可调电容，被配置为调节可调电容的任意波形发生器以及耦合到移相器的脉冲图形发生器，所述移相器被配置为 控制脉冲模式发生器。 在一个方面，可调电容是至少一个变容二极管。 另一方面，一对变容二极管由λ/ 4线分开，可调电容的输入和输出是交流耦合的，并且任意波形发生器被配置成通过高斯噪声信号输入到 一对变容二极管。 确定性抖动发生器可以耦合到脉冲图案发生器。 可以向模式发生器输入开路短线，确定性抖动内容数可调，可变长短线长度。
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5.发明授权Method and system for using statistical signatures for testing high-speed circuits 有权统计特征用于测试高速电路的方法和系统公开(公告)号：US07340660B2
公开(公告)日：2008-03-04
申请号：US10680679
申请日：2003-10-07
IPC分类号： G01R31/3193 , G01R31/316
CPC分类号： G01R31/31901 , G01R31/31707
摘要： A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.
摘要翻译： 公开了一种用于测试高速电路的方法和系统。 该方法和系统包括使用常规测试仪获得高速电路的高速统计特征。 该方法和系统还包括将高速电路的高速统计签名与预期签名进行比较。 因此，可以确定高速电路是否在期望的参数内起作用。
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6.发明授权Method for determining jitter of a signal in a serial link and high speed serial link 有权用于确定串行链路和高速串行链路中的信号抖动的方法公开(公告)号：US07295604B2
公开(公告)日：2007-11-13
申请号：US10720974
申请日：2003-11-24
IPC分类号： H04B3/46
CPC分类号： H04L25/068 , H04B3/462 , H04L1/205
摘要： The method for determining jitter of a signal in a serial link according to the invention comprising the following steps: First, a section of the signal transmitted via a transmission channel is sampled at different sampling times. The total number of edges in the section is determined. The neighboring sample values are analyzed and from that a statistical value is formed. From the statistical value and the total number of edges a figure of merit is determined. Finally, by means of a look-up table or a jitter-versus-figure of merit curve, the total jitter corresponding to the figure of merit is derived.
摘要翻译： 根据本发明的用于确定串行链路中的信号的抖动的方法包括以下步骤：首先，经由传输信道发送的信号的一部分在不同的采样时间被采样。 确定该部分中的边缘总数。 分析相邻的样本值，并从中形成统计值。 从统计值和边缘总数确定品质因数。 最后，通过查询表或优点曲线的抖动对数值，推导出与品质因数对应的总抖动。
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7.发明申请公开(公告)号：US20090146722A1
公开(公告)日：2009-06-11
申请号：US11953346
申请日：2007-12-10
CPC分类号： H03F3/45183 , H03F3/45744 , H03F2203/45652 , H03F2203/45681
摘要： In one embodiment a method is disclosed that includes applying a series of voltages to an input of an offset evaluation latch, detecting an offset voltage from the offset evaluation latch in response to the application of the series of voltages, and applying an offset compensation voltage to the input of a plurality of sampling latch in response to the detected offset voltage. In some embodiments a digital value can be assigned to the applied offset voltage. When the offset voltage is determined, it can be applied to a plurality sampling latches and a data stream can be received and clock and data recovery can be performed.
摘要翻译： 在一个实施例中，公开了一种方法，其包括将一系列电压施加到偏移评估锁存器的输入端，响应于所述一系列电压的应用来检测来自所述偏移评估锁存器的偏移电压，以及将偏移补偿电压施加到 响应于检测到的偏移电压而输入多个采样锁存器。 在一些实施例中，可以将数字值分配给所施加的偏移电压。 当确定偏移电压时，可以将其应用于多个采样锁存器，并且可以接收数据流，并且可以执行时钟和数据恢复。
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8.发明授权Dynamic measurement of communication channel characteristics using direct sequence spread spectrum (DSSS) systems, methods and program products 失效使用直接序列扩频（DSSS）系统，方法和程序产品对通信信道特性的动态测量公开(公告)号：US07088766B2
公开(公告)日：2006-08-08
申请号：US10014455
申请日：2001-12-14
CPC分类号： H04B1/707 , H04B1/7095
摘要： A DSSS system determines transmission reliability of a communication channel in real time. A DSSS transmitter (f0=1/T) generates a Pseudo Noise (PN) code and modulates a carrier source [cos. (2Σγc)] with a selected chip rate. The transmitter bandwidth is a direct function of the chip rate. The PN coded carrier signal is further modulated by a data signal [m(t)] to provide an output signal [s(t)] to a correlator via a communication channel for purposes of determining the transmission characteristic of the channel. The correlator running a variable length pseudo noise code combines the code and the carrier which relates the incoming data signal to a correlation value for detecting the data signal. The correlation value is compared to a threshold value based upon experience of reliable transmission of data through the communication channel. The value of the correlation value declines as the data is attenuated in the communication channel, thus, the band limiting effect of the communication can be determined by the change in the correlation value.
摘要翻译： DSSS系统实时确定通信信道的传输可靠性。 DSSS发射机（f 0 0 = 1 / T）产生伪噪声（PN）码，并调制载波源[cos。 （2Sigmagamma c））]。 发射机带宽是芯片速率的直接函数。 PN编码的载波信号被数据信号[m（t）]进一步调制，以通过通信信道向相关器提供输出信号[s（t）]，以便确定信道的传输特性。 运行可变长度伪噪声码的相关器将代码和将输入数据信号相关联的载波组合成用于检测数据信号的相关值。 基于通过通信信道可靠地传输数据的经验将相关值与阈值进行比较。 在通信信道中数据被衰减时，相关值的值下降，因此通信的频带限制效果可以通过相关值的变化来确定。
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公开(公告)号：US07279950B2
公开(公告)日：2007-10-09
申请号：US11235758
申请日：2005-09-27
IPC分类号： H03K3/00
CPC分类号： G06F1/04
摘要： A differential clock signal gating method and system is provided, wherein a clock buffer circuit control path develops a clock gating signal with a timing relationship to a clock signal. The clock gating signal gates a buffer on the clock buffer circuit controlled path in communication with the clock signal responsive to a first clock signal pulse negative half. The buffer provides second and successive clock signal pulses occurring immediately and sequentially after the first clock signal pulse as a buffer clock signal output to a second buffer stage in a second stage clock path, each having the nominal clock amplitude and the nominal clock pulse width of the clock signal without jitter.
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10.发明授权Circuit and method for reducing jitter in a PLL of high speed serial links 失效用于降低高速串行链路PLL的抖动的电路和方法公开(公告)号：US07042277B2
公开(公告)日：2006-05-09
申请号：US10685022
申请日：2003-10-14
IPC分类号： G01F1/10
CPC分类号： H03L7/10
摘要： Aspects for reducing jitter in a PLL of a high speed serial link include examining at least one parameter related to performance of a voltage controlled oscillator (VCO) in the PLL, and controlling adjustment of a supply voltage to the VCO based on the examining. A regulator control circuit performs the examining and controlling.
摘要翻译： 降低高速串行链路的PLL中的抖动的方面包括检查与PLL中的压控振荡器（VCO）的性能有关的至少一个参数，以及基于检查来控制对VCO的电源电压的调整。 调节器控制电路进行检查和控制。
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