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1.发明授权Method for determining jitter of a signal in a serial link and high speed serial link 有权用于确定串行链路和高速串行链路中的信号抖动的方法公开(公告)号：US07295604B2
公开(公告)日：2007-11-13
申请号：US10720974
申请日：2003-11-24
IPC分类号： H04B3/46
CPC分类号： H04L25/068 , H04B3/462 , H04L1/205
摘要： The method for determining jitter of a signal in a serial link according to the invention comprising the following steps: First, a section of the signal transmitted via a transmission channel is sampled at different sampling times. The total number of edges in the section is determined. The neighboring sample values are analyzed and from that a statistical value is formed. From the statistical value and the total number of edges a figure of merit is determined. Finally, by means of a look-up table or a jitter-versus-figure of merit curve, the total jitter corresponding to the figure of merit is derived.
摘要翻译： 根据本发明的用于确定串行链路中的信号的抖动的方法包括以下步骤：首先，经由传输信道发送的信号的一部分在不同的采样时间被采样。 确定该部分中的边缘总数。 分析相邻的样本值，并从中形成统计值。 从统计值和边缘总数确定品质因数。 最后，通过查询表或优点曲线的抖动对数值，推导出与品质因数对应的总抖动。
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公开(公告)号：US07512177B2
公开(公告)日：2009-03-31
申请号：US11828390
申请日：2007-07-26
IPC分类号： H04B3/46
CPC分类号： H04L25/068 , H04B3/462 , H04L1/205
摘要： Apparatuses and methods comprise a phase shifter, an adjustable capacitance configured to adjust a phase shift of said phase shifter, an arbitrary waveform generator configured to adjust the adjustable capacitance, and a pulse pattern generator coupled to the phase shifter, the phase shifter is configured to control the pulse pattern generator. In one aspect, an adjustable capacitance is at least one varactor diode. In another, a pair of varactor diodes are separated by λ/4 lines, an input and an output of the adjustable capacitance is AC-coupled, and the arbitrary waveform generator is configured to adjust the adjustable capacitance through a gaussian noise signal input to the pair of varactor diodes. A deterministic jitter generator may be coupled to the pulse pattern generator. An open-circuited stub line may be input to the pattern generator, a deterministic jitter content number adjustable varying stub line length.
摘要翻译： 装置和方法包括移相器，被配置为调整所述移相器的相移的可调电容，被配置为调节可调电容的任意波形发生器以及耦合到移相器的脉冲图形发生器，所述移相器被配置为 控制脉冲模式发生器。 在一个方面，可调电容是至少一个变容二极管。 另一方面，一对变容二极管由λ/ 4线分开，可调电容的输入和输出是交流耦合的，并且任意波形发生器被配置成通过高斯噪声信号输入到 一对变容二极管。 确定性抖动发生器可以耦合到脉冲图案发生器。 可以向模式发生器输入开路短线，确定性抖动内容数可调，可变长短线长度。
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公开(公告)号：US20080150599A1
公开(公告)日：2008-06-26
申请号：US11828390
申请日：2007-07-26
IPC分类号： H03K3/84
CPC分类号： H04L25/068 , H04B3/462 , H04L1/205
摘要： Apparatuses and methods comprise a phase shifter, an adjustable capacitance configured to adjust a phase shift of said phase shifter, an arbitrary waveform generator configured to adjust the adjustable capacitance, and a pulse pattern generator coupled to the phase shifter, the phase shifter is configured to control the pulse pattern generator. In one aspect, an adjustable capacitance is at least one varactor diode. In another, a pair of varactor diodes are separated by λ/4 lines, an input and an output of the adjustable capacitance is AC-coupled, and the arbitrary waveform generator is configured to adjust the adjustable capacitance through a gaussian noise signal input to the pair of varactor diodes. A deterministic jitter generator may be coupled to the pulse pattern generator. An open-circuited stub line may be input to the pattern generator, a deterministic jitter content number adjustable varying stub line length.
摘要翻译： 装置和方法包括移相器，被配置为调整所述移相器的相移的可调电容，被配置为调节可调电容的任意波形发生器以及耦合到移相器的脉冲图形发生器，所述移相器被配置为 控制脉冲模式发生器。 在一个方面，可调电容是至少一个变容二极管。 另一方面，一对变容二极管由λ/ 4线分开，可调电容的输入和输出是交流耦合的，并且任意波形发生器被配置成通过高斯噪声信号输入到 一对变容二极管。 确定性抖动发生器可以耦合到脉冲图案发生器。 可以向模式发生器输入开路短线，确定性抖动内容数可调，可变长短线长度。
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4.发明授权CML delay cell with linear rail-to-rail tuning range and constant output swing 有权CML延迟单元具有线性轨至轨调谐范围和恒定输出摆幅公开(公告)号：US07403057B2
公开(公告)日：2008-07-22
申请号：US11556882
申请日：2006-11-06
IPC分类号： H03H11/26
CPC分类号： H03K5/13 , H03K5/133 , H03K2005/00032 , H03K2005/00208
摘要： A current mode logic (CML) delay cell with linear rail-to-rail tuning range and constant output swing. The CML delay cell can include a tuning voltage input on a first and second transistor, contributing to a CML delay cell load, and a bias voltage input on a third transistor, as a current source I0, and a compensation circuit having switching point optimized inverters having a first plurality of transistors having a transconductance βpN and a second plurality of transistors having a transconductance βnN, wherein respective ratios of βnN/βpN determine an inverter switching point of respective switching point optimized inverters, the first and second plurality of transistors having gates coupled to the tuning voltage input of the CML delay cell, wherein the switching point optimized inverters are followed by weighted tail current sources M0N that supply additional currents to the current source I0 at a drain node of the third transistor.
摘要翻译： 具有线性轨至轨调谐范围和恒定输出摆幅的电流模式逻辑（CML）延迟单元。 CML延迟单元可以包括在第一和第二晶体管上的调谐电压输入，有助于CML延迟单元负载，以及作为电流源I 0的第三晶体管上的偏置电压输入，以及 具有开关点优化的反相器的补偿电路，其具有具有跨导βN N N的第一多个晶体管和具有跨导βN N N的第二多个晶体管，其中， 确定各个开关点优化的逆变器的逆变器切换点，第一和第二多个晶体管具有耦合到CML延迟单元的调谐电压输入的门 其中所述开关点优化的逆变器之后是在所述第三晶体管的漏极节点向所述电流源I SUB提供附加电流的加权尾电流源M 0N N。
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5.发明授权CML delay cell with linear rail-to-rail tuning range and constant output swing 失效CML延迟单元具有线性轨至轨调谐范围和恒定输出摆幅公开(公告)号：US07541855B2
公开(公告)日：2009-06-02
申请号：US12124384
申请日：2008-05-21
IPC分类号： H03H11/26
CPC分类号： H03K5/13 , H03K5/133 , H03K2005/00032 , H03K2005/00208
摘要： A current mode logic (CML) delay cell with linear rail-to-rail tuning range and constant output swing. The CML delay cell can include a tuning voltage input on a first and second transistor, contributing to a CML delay cell load, and a bias voltage input on a third transistor, as a current source I0, and a compensation circuit having switching point optimized inverters having a first plurality of transistors having a transconductance βpN and a second plurality of transistors having a transconductance βnN, wherein respective ratios of βnN/βpN determine an inverter switching point of respective switching point optimized inverters, the first and second plurality of transistors having gates coupled to the tuning voltage input of the CML delay cell, wherein the switching point optimized inverters are followed by weighted tail current sources M0N that supply additional currents to the current source I0 at a drain node of the third transistor.
摘要翻译： 具有线性轨至轨调谐范围和恒定输出摆幅的电流模式逻辑（CML）延迟单元。 CML延迟单元可以包括在第一和第二晶体管上的调谐电压输入，有助于CML延迟单元负载，以及作为电流源I0在第三晶体管上输入的偏置电压，以及具有开关点优化的逆变器的补偿电路 具有跨导betapN的第一多个晶体管和具有跨导betanN的第二多个晶体管，其中，betanN / betapN的各自比例确定各个开关点优化的反相器的反相器切换点，第一和第二多个晶体管具有栅极耦合 到CML延迟单元的调谐电压输入，其中开关点优化的反相器之后是在第三晶体管的漏极节点向电流源I0提供附加电流的加权尾电流源M0N。
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6.发明授权公开(公告)号：US07839221B2
公开(公告)日：2010-11-23
申请号：US12132960
申请日：2008-06-04
IPC分类号： H03L7/00
摘要： A phase locked loop (PLL) which includes a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and generating a digital value representing the phase difference between the reference signal and the oscillator signal. The PLL further includes a state machine for phase acquisition that is capable of generating a control value depending on the digital value, and a controllable oscillator that is capable of generating the oscillator signal depending on the control value.
摘要翻译： 一种锁相环（PLL），其包括与时间数字转换器耦合的相位频率检测器，其能够将参考信号与振荡器信号进行比较，并产生表示参考信号和振荡器信号之间的相位差的数字值。 PLL还包括能够根据数字值产生控制值的相位获取状态机，以及能够根据控制值产生振荡器信号的可控振荡器。
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7.发明申请PHASE LOCKED LOOP AND METHOD FOR ADJUSTING THE FREQUENCY AND PHASE IN THE PHASE LOCKED LOOP 有权相位锁定环路和相位锁定环路中的频率和相位调整方法公开(公告)号：US20080246522A1
公开(公告)日：2008-10-09
申请号：US12132960
申请日：2008-06-04
IPC分类号： H03L7/08
摘要： A phase locked loop (PLL) which includes a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and generating a digital value representing the phase difference between the reference signal and the oscillator signal. The PLL further includes a state machine for phase acquisition that is capable of generating a control value depending on the digital value, and a controllable oscillator that is capable of generating the oscillator signal depending on the control value.
摘要翻译： 一种锁相环（PLL），其包括与时间数字转换器耦合的相位频率检测器，其能够将参考信号与振荡器信号进行比较，并产生表示参考信号和振荡器信号之间的相位差的数字值。 PLL还包括能够根据数字值产生控制值的相位获取状态机，以及能够根据控制值产生振荡器信号的可控振荡器。
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8.发明授权公开(公告)号：US07403073B2
公开(公告)日：2008-07-22
申请号：US11469423
申请日：2006-08-31
IPC分类号： H03L7/00
摘要： A phase locked loop (PLL) which includes a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and generating a digital value representing the phase difference between the reference signal and the oscillator signal. The PLL further includes a state machine for phase acquisition that is capable of generating a control value depending on the digital value, and a controllable oscillator that is capable of generating the oscillator signal depending on the control value.
摘要翻译： 一种锁相环（PLL），其包括与时间数字转换器耦合的相位频率检测器，其能够将参考信号与振荡器信号进行比较，并产生表示参考信号和振荡器信号之间的相位差的数字值。 PLL还包括能够根据数字值产生控制值的相位获取状态机，以及能够根据控制值产生振荡器信号的可控振荡器。
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公开(公告)号：US08717138B2
公开(公告)日：2014-05-06
申请号：US13557807
申请日：2012-07-25
CPC分类号： H03H7/185
摘要： An inductor including a primary coil coaxially arranged and operated in parallel with isolated secondary coils each including at least one loop winding with two open-circuited ports. At least one phase shifting device is arranged between open-circuited ports of at least one secondary coil. A method to operate an inductor by combining primary and secondary coils with phase shifting devices to get a wide tuning range is also provided. The method includes the step of phase shifting open-circuited ports of at least one secondary coil.
摘要翻译： 一种电感器，包括与隔离次级线圈并联布置并并联操作的初级线圈，每个线圈包括至少一个具有两个开路端口的环绕组。 至少一个相移装置布置在至少一个次级线圈的开路端口之间。 还提供了通过将初级和次级线圈与相移装置组合以获得宽的调谐范围来操作电感器的方法。 该方法包括相移至少一个次级线圈的开路端口的步骤。
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公开(公告)号：US20130021129A1
公开(公告)日：2013-01-24
申请号：US13557807
申请日：2012-07-25
IPC分类号： H01F27/28
CPC分类号： H03H7/185
摘要： An inductor including a primary coil coaxially arranged and operated in parallel with isolated secondary coils each including at least one loop winding with two open-circuited ports. At least one phase shifting device is arranged between open-circuited ports of at least one secondary coil. A method to operate an inductor by combining primary and secondary coils with phase shifting devices to get a wide tuning range is also provided. The method includes the step of phase shifting open-circuited ports of at least one secondary coil.
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