公开(公告)号：US07310268B2

公开(公告)日：2007-12-18

申请号：US11115301

申请日：2005-04-27

申请人： Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

发明人： Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/0408 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/7881

摘要： A float gate memory device comprises a bottom word line, a float channel layer formed on the bottom word line and kept at a floating state, a float gate, and a top word line formed on the float gate in parallel with the bottom word line. In the float gate formed on the float channel, data are stored. Here, data are written in the float gate depending on levels of the bottom word line and the top word line, and different channel resistances are induced to the float channel depending on polarity states of charges stored in the float gate, so that data are read. As a result, in the float gate memory device, a retention characteristic is improved, and cell integrated capacity is also increased due to a plurality of float gate cell arrays deposited vertically using a plurality of cell oxide layers.

摘要翻译： 浮动栅极存储器件包括底部字线，形成在底部字线上并保持在浮置状态的浮动沟道层，浮动栅极和形成在浮动栅极上的与底部字线平行的顶部字线。 在浮动通道上形成的浮动门中，存储数据。 这里，根据底部字线和顶部字线的电平，将数据写入浮动栅极，并且根据存储在浮动栅极中的电荷的极性状态，将不同的通道电阻感应到浮动通道，从而读取数据 。 结果，在浮栅存储器件中，由于使用多个单元氧化物层垂直淀积的多个浮栅单元阵列，保持特性得到改善，并且单元集成能力也增加。

公开(公告)号：US07126185B2

公开(公告)日：2006-10-24

申请号：US11115135

申请日：2005-04-27

申请人： Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

发明人： Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

IPC分类号： H01L29/788

CPC分类号： G11C16/0483 ,  G11C16/0466 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/8616

摘要： A charge trap insulator memory device comprises a plurality of memory cells connected serially, a first switching device, and a second switching device. In the plurality of memory cells, data applied through a bit line depending on potentials applied to a top word line and a bottom word line are stored in a charge trap insulator or the data stored in the charge trap insulator are outputted to the bit line. The first switching element selectively connects the plurality of memory cells to the bit line in response to a first selecting signal. The second switching element selectively connects the plurality of memory cells to a sensing line in response to a second selecting signal.

公开(公告)号：US08035146B2

公开(公告)日：2011-10-11

申请号：US12820092

申请日：2010-06-21

申请人： Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

发明人： Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

IPC分类号： H01L27/115

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L21/84 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7841

摘要： A nonvolatile ferroelectric memory device includes a plurality of unit cell arrays, wherein each of the plurality of unit cell arrays includes: a bottom word line; a plurality of insulating layers formed on the bottom word line, respectively; a floating channel layer comprising a plurality of channel regions located on the plurality of insulating layers and a plurality of drain and source regions which are alternately electrically connected in series to the plurality of channel regions; a plurality of ferroelectric layers formed respectively on the plurality of channel regions of the floating channel layer; and a plurality of word lines formed on the plurality of ferroelectric layers, respectively. The unit cell array reads and writes a plurality of data by inducing different channel resistance to the plurality of channel regions depending on polarity states of the plurality of ferroelectric layers.

摘要翻译： 非易失性铁电存储器件包括多个单元阵列，其中多个单元阵列中的每一个包括：底部字线; 分别形成在底部字线上的多个绝缘层; 浮动沟道层，包括位于所述多个绝缘层上的多个沟道区和与所述多个沟道区交替电连接的多个漏极和源极区; 分别形成在所述浮动沟道层的所述多个沟道区上的多个铁电层; 以及分别形成在多个铁电体层上的多个字线。 根据多个铁电层的极性状态，单元阵列通过对多个沟道区域引起不同的沟道电阻来读取和写入多个数据。

公开(公告)号：US07741668B2

公开(公告)日：2010-06-22

申请号：US11717081

申请日：2007-03-13

申请人： Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

发明人： Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

IPC分类号： H01L29/94

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L21/84 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7841

摘要： A nonvolatile ferroelectric memory device is provided so as to control read/write operations of a nonvolatile memory cell using a channel resistance of the memory cell which is differentiated by polarity states of a ferroelectric material. In the memory device, an insulating layer is formed on a bottom word line, and a floating channel layer comprising a N-type drain region, a P-type channel region and a N-type source region is formed on the insulating layer. Then, a ferroelectric layer is formed on the floating channel layer, and a word line is formed on the ferroelectric layer. As a result, the resistance state induced to the channel region is controlled depending on the polarity of the ferroelectric layer, thereby regulating the read/write operations of the memory cell array.

摘要翻译： 提供非易失性铁电存储器件，以便使用由铁电材料的极性状态区分的存储单元的沟道电阻来控制非易失性存储单元的读/写操作。 在存储器件中，在底部字线上形成绝缘层，并且在绝缘层上形成包括N型漏极区，P型沟道区和N型源极区的浮动沟道层。 然后，在浮动沟道层上形成铁电体层，在铁电体层上形成字线。 结果，根据铁电层的极性来控制感应到沟道区的电阻状态，从而调节存储单元阵列的读/写操作。

公开(公告)号：US07728369B2

公开(公告)日：2010-06-01

申请号：US11717145

申请日：2007-03-13

申请人： Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

发明人： Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

IPC分类号： H01L29/94

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L21/84 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7841

摘要： A nonvolatile ferroelectric memory device is provided so as to control read/write operations of a nonvolatile memory cell using a channel resistance of the memory cell which is differentiated by polarity states of a ferroelectric material. In the memory device, an insulating layer is formed on a bottom word line, and a floating channel layer comprising a N-type drain region, a P-type channel region and a N-type source region is formed on the insulating layer. Then, a ferroelectric layer is formed on the floating channel layer, and a word line is formed on the ferroelectric layer. As a result, the resistance state induced to the channel region is controlled depending on the polarity of the ferroelectric layer, thereby regulating the read/write operations of the memory cell array.

公开(公告)号：US07274593B2

公开(公告)日：2007-09-25

申请号：US11115302

申请日：2005-04-27

申请人： Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

发明人： Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

IPC分类号： G11C16/04

CPC分类号： G11C11/22 ,  H01L27/11502 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391

摘要： A nonvolatile ferroelectric memory device is provided so as to control read/write operations of a nonvolatile memory cell using a channel resistance of the memory cell which is differentiated by polarity states of a ferroelectric material. In the memory device, an insulating layer is formed on a bottom word line, and a floating channel layer comprising a P-type drain region, a P-type channel region and a P-type source region is formed on the insulating layer. Then, a ferroelectric layer is formed on the floating channel layer, and a word line is formed on the ferroelectric layer. As a result, the resistance state induced to the channel region is controlled depending on the polarity of the ferroelectric layer, thereby regulating the read/write operations of the memory cell array.

摘要翻译： 提供非易失性铁电存储器件，以便使用由铁电材料的极性状态区分的存储单元的沟道电阻来控制非易失性存储单元的读/写操作。 在存储器件中，在底部字线上形成绝缘层，在绝缘层上形成包括P型漏极区域，P型沟道区域和P型源极区域的浮动沟道层。 然后，在浮动沟道层上形成铁电体层，在铁电体层上形成字线。 结果，根据铁电层的极性来控制感应到沟道区的电阻状态，从而调节存储单元阵列的读/写操作。

公开(公告)号：US07902963B2

公开(公告)日：2011-03-08

申请号：US12178452

申请日：2008-07-23

申请人： Hee Bok Kang ,  Jin Hong Ahn

发明人： Hee Bok Kang ,  Jin Hong Ahn

IPC分类号： H04Q5/22

CPC分类号： G06K19/0723 ,  G06K19/0701

摘要： A RFID device has a nonvolatile ferroelectric memory including a memory cell array area supplied only with a high voltage and a peripheral area supplied with a low voltage, thereby reducing power consumption. The RFID device includes an antenna adapted and configured to transceive a radio frequency signal from an external communication apparatus, an analog block adapted and configured to generate a power voltage in response to the radio frequency signal received from the antenna, a digital block adapted and configured to receive the power voltage from the analog block, transmit a response signal to the analog block and output a memory control signal, and a memory adapted and configured to generate a high voltage with the power voltage and access data in response to the memory control signal.

摘要翻译： RFID装置具有非易失性铁电存储器，其包括仅供给高电压的存储单元阵列区域和供给低电压的周边区域，从而降低功耗。 RFID设备包括适于并配置为收发来自外部通信设备的射频信号的天线，适于并配置为响应于从天线接收的射频信号而产生电力电压的模拟块，适配和配置的数字块 从模拟块接收电源电压，将响应信号发送到模拟块并输出存储器控制信号，以及存储器，其被配置成响应于存储器控制信号而产生具有电源电压和访问数据的高电压 。

公开(公告)号：US07602658B2

公开(公告)日：2009-10-13

申请号：US12045636

申请日：2008-03-10

申请人： Hee Bok Kang ,  Jin Hong Ahn

发明人： Hee Bok Kang ,  Jin Hong Ahn

IPC分类号： G11C7/00

CPC分类号： G11C11/22 ,  G11C7/16 ,  G11C8/10

摘要： A RFID device having a nonvolatile ferroelectric memory regulates bit line capacitance to optimize a bit line sensing margin and minimize power consumption. The RFID device having an analog block adapted and configured to transmit and receive a radio frequency signal to/from an external communication apparatus, a digital block adapted and configured to receive a power voltage and the radio frequency signal from the analog block, transmit a response signal to the analog block and output a memory control signal, and a memory adapted and configured to store data and regulate bit line capacitance.

摘要翻译： 具有非易失性铁电存储器的RFID装置调节位线电容以优化位线感测裕度并最小化功耗。 RFID装置具有适于并被配置为向/从外部通信装置发送和接收射频信号的模拟块，适于并被配置为从模拟块接收电力电压和射频信号的数字块，发送响应 信号到模拟块并输出存储器控制信号，以及适配和配置为存储数据并调节位线电容的存储器。

公开(公告)号：US07417528B2

公开(公告)日：2008-08-26

申请号：US11325486

申请日：2006-01-05

申请人： Hee Bok Kang ,  Jin Hong Ahn

发明人： Hee Bok Kang ,  Jin Hong Ahn

IPC分类号： H04Q5/22

CPC分类号： G06K19/0723 ,  G06K19/0701

摘要： A RFID device has a nonvolatile ferroelectric memory including a memory cell array area supplied only with a high voltage and a peripheral area supplied with a low voltage, thereby reducing power consumption. The RFID device includes an antenna adapted and configured to transceive a radio frequency signal from an external communication apparatus, an analog block adapted and configured to generate a power voltage in response to the radio frequency signal received from the antenna, a digital block adapted and configured to receive the power voltage from the analog block, transmit a response signal to the analog block and output a memory control signal, and a memory adapted and configured to generate a high voltage with the power voltage and access data in response to the memory control signal.

摘要翻译： RFID装置具有非易失性铁电存储器，其包括仅供给高电压的存储单元阵列区域和供给低电压的周边区域，从而降低功耗。 RFID设备包括适于并配置为收发来自外部通信设备的射频信号的天线，适于并配置为响应于从天线接收的射频信号而产生电力电压的模拟块，适配和配置的数字块 从模拟块接收电源电压，将响应信号发送到模拟块并输出存储器控制信号，以及存储器，其被配置为响应于存储器控制信号而产生具有电源电压和访问数据的高电压 。

公开(公告)号：US07366039B2

公开(公告)日：2008-04-29

申请号：US11320986

申请日：2005-12-30

申请人： Hee Bok Kang ,  Jin Hong Ahn

发明人： Hee Bok Kang ,  Jin Hong Ahn

IPC分类号： G11C7/00

CPC分类号： G11C11/22 ,  G11C7/16 ,  G11C8/10

摘要： A RFID device having a nonvolatile ferroelectric memory regulates bit line capacitance to optimize a bit line sensing margin and minimize power consumption. The RFID device having an analog block adapted and configured to transmit and receive a radio frequency signal to/from an external communication apparatus, a digital block adapted and configured to receive a power voltage and the radio frequency signal from the analog block, transmit a response signal to the analog block and output a memory control signal, and a memory adapted and configured to store data and regulate bit line capacitance.

摘要翻译： 具有非易失性铁电存储器的RFID装置调节位线电容以优化位线感测裕度并最小化功耗。 RFID装置具有适于并被配置为向/从外部通信装置发送和接收射频信号的模拟块，适于并被配置为从模拟块接收电力电压和射频信号的数字块，发送响应 信号到模拟块并输出存储器控制信号，以及适配和配置为存储数据并调节位线电容的存储器。