公开(公告)号：US07653170B2

公开(公告)日：2010-01-26

申请号：US11440481

申请日：2006-05-25

申请人： Heinz Mattes ,  Thomas Piorek ,  Sebastian Sattler ,  Olaf Stroeble

发明人： Heinz Mattes ,  Thomas Piorek ,  Sebastian Sattler ,  Olaf Stroeble

IPC分类号： G04F10/04

CPC分类号： G01R31/31922 ,  G01R31/31937 ,  G04F10/04 ,  G04F10/06

摘要： An electrical circuit used for measuring times is disclosed. In one embodiment, the electrical circuit has a counter, a decoder and a multiplicity of time trap elements. At least the counter and the time trap elements are located together on an integrated semiconductor component. Each time trap element has a data input, a clock input, a delay output and a output port. The time trap element contains a delay element and a flip flop. The delay element outputs a signal change at the data input with a time delay at the delay output. The flip flop has a data input, a clock input and an output port, the data inputs, the clock inputs and the output ports of the flip flop and of the time trap element being connected to one another. The time trap elements are connected as ring oscillator.

摘要翻译： 公开了一种用于测量时间的电路。 在一个实施例中，电路具有计数器，解码器和多个时间陷波元件。 至少计数器和时间陷阱元件一起位于集成半导体部件上。 每次陷阱元件都具有数据输入，时钟输入，延迟输出和输出端口。 时间陷阱元件包含延迟元件和触发器。 延迟元件在延迟输出端以时间延迟输出数据输入端的信号变化。 触发器具有数据输入，时钟输入和输出端口，触发器的数据输入，时钟输入和输出端口以及时间陷阱元件彼此连接。 时间陷阱元件连接为环形振荡器。

公开(公告)号：US20060274607A1

公开(公告)日：2006-12-07

申请号：US11440481

申请日：2006-05-25

申请人： Heinz Mattes ,  Thomas Piorek ,  Sebastian Sattler ,  Olaf Stroeble

发明人： Heinz Mattes ,  Thomas Piorek ,  Sebastian Sattler ,  Olaf Stroeble

IPC分类号： G04F10/00

CPC分类号： G01R31/31922 ,  G01R31/31937 ,  G04F10/04 ,  G04F10/06

摘要： An electrical circuit used for measuring times is disclosed. In one embodiment, the electrical circuit has a counter, a decoder and a multiplicity of time trap elements. At least the counter and the time trap elements are located together on an integrated semiconductor component. Each time trap element has a data input, a clock input, a delay output and a output port. The time trap element contains a delay element and a flip flop. The delay element outputs a signal change at the data input with a time delay at the delay output. The flip flop has a data input, a clock input and an output port, the data inputs, the clock inputs and the output ports of the flip flop and of the time trap element being connected to one another. The time trap elements are connected as ring oscillator.

摘要翻译： 公开了一种用于测量时间的电路。 在一个实施例中，电路具有计数器，解码器和多个时间陷波元件。 至少计数器和时间陷阱元件一起位于集成半导体部件上。 每次陷阱元件都具有数据输入，时钟输入，延迟输出和输出端口。 时间陷阱元件包含延迟元件和触发器。 延迟元件在延迟输出端以时间延迟输出数据输入端的信号变化。 触发器具有数据输入，时钟输入和输出端口，触发器的数据输入，时钟输入和输出端口以及时间陷阱元件彼此连接。 时间陷阱元件连接为环形振荡器。

公开(公告)号：US06212102B1

公开(公告)日：2001-04-03

申请号：US09250364

申请日：1999-02-12

申请人： Georg Georgakos ,  Martin Bloch ,  Kai Kasprick ,  Thomas Kern ,  Jürgen Peter ,  Thomas Piorek

发明人： Georg Georgakos ,  Martin Bloch ,  Kai Kasprick ,  Thomas Kern ,  Jürgen Peter ,  Thomas Piorek

IPC分类号： G11C1604

CPC分类号： G11C16/3427 ,  G11C16/0433 ,  G11C16/10

摘要： An EEPROM with two-transistor memory cells with source-side selection, and a method for triggering such a EEPROM are described. The EEPROM and the method are distinguished in that the programming voltage required to program a memory cell is delivered via a source line. As a result the EEPROM can be protected in a simple way against unintended loss of the data stored in it.

摘要翻译： 描述了具有源侧选择的双晶体管存储单元的EEPROM和用于触发这种EEPROM的方法。 EEPROM和方法的区别在于，通过源极线传送编程存储器单元所需的编程电压。 因此，EEPROM可以以简单的方式进行保护，以防止存储在其中的数据的意外丢失。

公开(公告)号：US06667609B2

公开(公告)日：2003-12-23

申请号：US10262178

申请日：2002-09-30

申请人： Michael Verbeck ,  Thomas Piorek

发明人： Michael Verbeck ,  Thomas Piorek

IPC分类号： G05F316

CPC分类号： G05F3/262

摘要： A current generating device is characterized in that it is configured for, in response to a predetermined event, temporarily impresses a current, which is modified in comparison to the usual current, onto a device connected to the current generating device. In addition, a voltage generating device is configured for, in response to the predetermined event, temporarily applying a voltage, which is modified in comparison to the usual voltage, to the device connected to the voltage generating device.

摘要翻译： 电流产生装置的特征在于，其被配置为响应于预定事件，临时将与通常电流相比修改的电流施加到连接到当前发电装置的装置上。 此外，电压产生装置被配置为响应于预定事件，临时将与通常电压相比修改的电压施加到连接到电压产生装置的装置。